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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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67a82dbc0a
Tegra186 and later support 40 bits of address space. Additional registers need to be programmed to store the full 40 bits of push buffer addresses. Since command stream gathers can also reside in buffers in a 40-bit address space, a new variant of the GATHER opcode is also introduced. It takes two parameters: the first parameter contains the lower 32 bits of the address and the second parameter contains bits 32 to 39. Signed-off-by: Thierry Reding <treding@nvidia.com>
149 lines
4.0 KiB
C
149 lines
4.0 KiB
C
/*
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* Tegra host1x Register Offsets for Tegra194
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*
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* Copyright (c) 2018 NVIDIA Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __HOST1X_HOST1X07_HARDWARE_H
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#define __HOST1X_HOST1X07_HARDWARE_H
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#include <linux/types.h>
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#include <linux/bitops.h>
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#include "hw_host1x07_channel.h"
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#include "hw_host1x07_uclass.h"
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#include "hw_host1x07_vm.h"
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#include "hw_host1x07_hypervisor.h"
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static inline u32 host1x_class_host_wait_syncpt(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_wait_syncpt_indx_f(indx)
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| host1x_uclass_wait_syncpt_thresh_f(threshold);
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}
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static inline u32 host1x_class_host_load_syncpt_base(
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unsigned indx, unsigned threshold)
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{
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return host1x_uclass_load_syncpt_base_base_indx_f(indx)
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| host1x_uclass_load_syncpt_base_value_f(threshold);
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}
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static inline u32 host1x_class_host_wait_syncpt_base(
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unsigned indx, unsigned base_indx, unsigned offset)
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{
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return host1x_uclass_wait_syncpt_base_indx_f(indx)
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| host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
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| host1x_uclass_wait_syncpt_base_offset_f(offset);
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}
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static inline u32 host1x_class_host_incr_syncpt_base(
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unsigned base_indx, unsigned offset)
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{
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return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
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| host1x_uclass_incr_syncpt_base_offset_f(offset);
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}
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static inline u32 host1x_class_host_incr_syncpt(
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unsigned cond, unsigned indx)
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{
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return host1x_uclass_incr_syncpt_cond_f(cond)
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| host1x_uclass_incr_syncpt_indx_f(indx);
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}
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static inline u32 host1x_class_host_indoff_reg_write(
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unsigned mod_id, unsigned offset, bool auto_inc)
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{
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u32 v = host1x_uclass_indoff_indbe_f(0xf)
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| host1x_uclass_indoff_indmodid_f(mod_id)
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| host1x_uclass_indoff_indroffset_f(offset);
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if (auto_inc)
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v |= host1x_uclass_indoff_autoinc_f(1);
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return v;
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}
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static inline u32 host1x_class_host_indoff_reg_read(
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unsigned mod_id, unsigned offset, bool auto_inc)
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{
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u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
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| host1x_uclass_indoff_indroffset_f(offset)
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| host1x_uclass_indoff_rwn_read_v();
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if (auto_inc)
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v |= host1x_uclass_indoff_autoinc_f(1);
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return v;
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}
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/* cdma opcodes */
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static inline u32 host1x_opcode_setclass(
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unsigned class_id, unsigned offset, unsigned mask)
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{
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return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
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}
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static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
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{
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return (1 << 28) | (offset << 16) | count;
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}
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static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
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{
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return (2 << 28) | (offset << 16) | count;
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}
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static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
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{
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return (3 << 28) | (offset << 16) | mask;
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}
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static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
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{
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return (4 << 28) | (offset << 16) | value;
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}
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static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
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{
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return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
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host1x_class_host_incr_syncpt(cond, indx));
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}
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static inline u32 host1x_opcode_restart(unsigned address)
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{
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return (5 << 28) | (address >> 4);
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}
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static inline u32 host1x_opcode_gather(unsigned count)
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{
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return (6 << 28) | count;
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}
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static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | count;
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}
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static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
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{
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return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
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}
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static inline u32 host1x_opcode_gather_wide(unsigned count)
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{
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return (12 << 28) | count;
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}
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#define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
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#endif
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