Linus Torvalds baeedc7158 Merge branch 'prep-for-5level' ... Merge 5-level page table prep from Kirill Shutemov: "Here's relatively low-risk part of 5-level paging patchset. Merging it now will make x86 5-level paging enabling in v4.12 easier. The first patch is actually x86-specific: detect 5-level paging support. It boils down to single define. The rest of patchset converts Linux MMU abstraction from 4- to 5-level paging. Enabling of new abstraction in most cases requires adding single line of code in arch-specific code. The rest is taken care by asm-generic/. Changes to mm/ code are mostly mechanical: add support for new page table level -- p4d_t -- where we deal with pud_t now. v2: - fix build on microblaze (Michal); - comment for __ARCH_HAS_5LEVEL_HACK in kasan_populate_zero_shadow(); - acks from Michal" * emailed patches from Kirill A Shutemov <kirill.shutemov@linux.intel.com>: mm: introduce __p4d_alloc() mm: convert generic code to 5-level paging asm-generic: introduce <asm-generic/pgtable-nop4d.h> arch, mm: convert all architectures to use 5level-fixup.h asm-generic: introduce __ARCH_USE_5LEVEL_HACK asm-generic: introduce 5level-fixup.h x86/cpufeature: Add 5-level paging detection		2017-03-10 08:59:07 -08:00
..
32	arch, mm: convert all architectures to use 5level-fixup.h	2017-03-09 11:48:47 -08:00
64	Merge branch 'prep-for-5level'	2017-03-10 08:59:07 -08:00
pgalloc.h	powerpc/mm/radix: Flush page walk cache when freeing page table	2016-06-10 16:14:52 +10:00
pgtable.h	powerpc/mm: Move PTE bits from generic functions to hash64 functions.	2015-12-14 15:19:08 +11:00