mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 21:06:39 +07:00
fa06920a3e
The File-backed Storage Gadget (g_file_storage) gadget has been replaced with Mass Storage Gadget (g_mass_storage) which uses the composite framework. This commit removes g_file_storage (and most references to it). Signed-off-by: Michal Nazarewicz <mina86@mina86.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Felipe Balbi <balbi@ti.com>
497 lines
18 KiB
C
497 lines
18 KiB
C
/*
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* linux/drivers/usb/gadget/pxa27x_udc.h
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* Intel PXA27x on-chip full speed USB device controller
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*
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* Inspired by original driver by Frank Becker, David Brownell, and others.
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* Copyright (C) 2008 Robert Jarzmik
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef __LINUX_USB_GADGET_PXA27X_H
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#define __LINUX_USB_GADGET_PXA27X_H
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#include <linux/types.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/usb/otg.h>
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/*
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* Register definitions
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*/
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/* Offsets */
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#define UDCCR 0x0000 /* UDC Control Register */
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#define UDCICR0 0x0004 /* UDC Interrupt Control Register0 */
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#define UDCICR1 0x0008 /* UDC Interrupt Control Register1 */
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#define UDCISR0 0x000C /* UDC Interrupt Status Register 0 */
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#define UDCISR1 0x0010 /* UDC Interrupt Status Register 1 */
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#define UDCFNR 0x0014 /* UDC Frame Number Register */
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#define UDCOTGICR 0x0018 /* UDC On-The-Go interrupt control */
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#define UP2OCR 0x0020 /* USB Port 2 Output Control register */
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#define UP3OCR 0x0024 /* USB Port 3 Output Control register */
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#define UDCCSRn(x) (0x0100 + ((x)<<2)) /* UDC Control/Status register */
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#define UDCBCRn(x) (0x0200 + ((x)<<2)) /* UDC Byte Count Register */
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#define UDCDRn(x) (0x0300 + ((x)<<2)) /* UDC Data Register */
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#define UDCCRn(x) (0x0400 + ((x)<<2)) /* UDC Control Register */
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#define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
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#define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation
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Protocol Port Support */
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#define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol
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Support */
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#define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol
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Enable */
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#define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
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#define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
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#define UDCCR_ACN_S 11
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#define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
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#define UDCCR_AIN_S 8
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#define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface
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Setting Number */
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#define UDCCR_AAISN_S 5
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#define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active
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Configuration */
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#define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration
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Error */
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#define UDCCR_UDR (1 << 2) /* UDC Resume */
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#define UDCCR_UDA (1 << 1) /* UDC Active */
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#define UDCCR_UDE (1 << 0) /* UDC Enable */
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#define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
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#define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
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#define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
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#define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
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#define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
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#define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
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#define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
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#define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
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#define UDCICR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
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#define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
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#define UDCISR1_IRCC (1 << 31) /* IntReq - Configuration Change */
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#define UDCISR1_IRSOF (1 << 30) /* IntReq - Start of Frame */
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#define UDCISR1_IRRU (1 << 29) /* IntReq - Resume */
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#define UDCISR1_IRSU (1 << 28) /* IntReq - Suspend */
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#define UDCISR1_IRRS (1 << 27) /* IntReq - Reset */
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#define UDCISR_INT_MASK (UDCICR_FIFOERR | UDCICR_PKTCOMPL)
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#define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
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#define UDCOTGICR_IEXR (1 << 17) /* Extra Transceiver Interrupt
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Rising Edge Interrupt Enable */
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#define UDCOTGICR_IEXF (1 << 16) /* Extra Transceiver Interrupt
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Falling Edge Interrupt Enable */
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#define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge
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Interrupt Enable */
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#define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge
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Interrupt Enable */
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#define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge
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Interrupt Enable */
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#define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge
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Interrupt Enable */
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#define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge
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Interrupt Enable */
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#define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge
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Interrupt Enable */
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#define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising
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Edge Interrupt Enable */
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#define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling
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Edge Interrupt Enable */
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#define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge
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Interrupt Enable */
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#define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge
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Interrupt Enable */
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/* Host Port 2 field bits */
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#define UP2OCR_CPVEN (1 << 0) /* Charge Pump Vbus Enable */
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#define UP2OCR_CPVPE (1 << 1) /* Charge Pump Vbus Pulse Enable */
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/* Transceiver enablers */
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#define UP2OCR_DPPDE (1 << 2) /* D+ Pull Down Enable */
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#define UP2OCR_DMPDE (1 << 3) /* D- Pull Down Enable */
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#define UP2OCR_DPPUE (1 << 4) /* D+ Pull Up Enable */
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#define UP2OCR_DMPUE (1 << 5) /* D- Pull Up Enable */
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#define UP2OCR_DPPUBE (1 << 6) /* D+ Pull Up Bypass Enable */
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#define UP2OCR_DMPUBE (1 << 7) /* D- Pull Up Bypass Enable */
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#define UP2OCR_EXSP (1 << 8) /* External Transceiver Speed Control */
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#define UP2OCR_EXSUS (1 << 9) /* External Transceiver Speed Enable */
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#define UP2OCR_IDON (1 << 10) /* OTG ID Read Enable */
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#define UP2OCR_HXS (1 << 16) /* Transceiver Output Select */
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#define UP2OCR_HXOE (1 << 17) /* Transceiver Output Enable */
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#define UP2OCR_SEOS (1 << 24) /* Single-Ended Output Select */
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#define UDCCSR0_ACM (1 << 9) /* Ack Control Mode */
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#define UDCCSR0_AREN (1 << 8) /* Ack Response Enable */
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#define UDCCSR0_SA (1 << 7) /* Setup Active */
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#define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
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#define UDCCSR0_FST (1 << 5) /* Force Stall */
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#define UDCCSR0_SST (1 << 4) /* Sent Stall */
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#define UDCCSR0_DME (1 << 3) /* DMA Enable */
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#define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
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#define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
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#define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
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#define UDCCSR_DPE (1 << 9) /* Data Packet Error */
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#define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
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#define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
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#define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
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#define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
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#define UDCCSR_FST (1 << 5) /* Force STALL */
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#define UDCCSR_SST (1 << 4) /* Sent STALL */
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#define UDCCSR_DME (1 << 3) /* DMA Enable */
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#define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
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#define UDCCSR_PC (1 << 1) /* Packet Complete */
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#define UDCCSR_FS (1 << 0) /* FIFO needs service */
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#define UDCCONR_CN (0x03 << 25) /* Configuration Number */
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#define UDCCONR_CN_S 25
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#define UDCCONR_IN (0x07 << 22) /* Interface Number */
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#define UDCCONR_IN_S 22
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#define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
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#define UDCCONR_AISN_S 19
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#define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
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#define UDCCONR_EN_S 15
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#define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
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#define UDCCONR_ET_S 13
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#define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
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#define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
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#define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
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#define UDCCONR_ET_NU (0x00 << 13) /* Not used */
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#define UDCCONR_ED (1 << 12) /* Endpoint Direction */
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#define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
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#define UDCCONR_MPS_S 2
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#define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
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#define UDCCONR_EE (1 << 0) /* Endpoint Enable */
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#define UDCCR_MASK_BITS (UDCCR_OEN | UDCCR_SMAC | UDCCR_UDR | UDCCR_UDE)
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#define UDCCSR_WR_MASK (UDCCSR_DME | UDCCSR_FST)
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#define UDC_FNR_MASK (0x7ff)
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#define UDC_BCR_MASK (0x3ff)
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/*
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* UDCCR = UDC Endpoint Configuration Registers
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* UDCCSR = UDC Control/Status Register for this EP
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* UDCBCR = UDC Byte Count Remaining (contents of OUT fifo)
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* UDCDR = UDC Endpoint Data Register (the fifo)
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*/
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#define ofs_UDCCR(ep) (UDCCRn(ep->idx))
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#define ofs_UDCCSR(ep) (UDCCSRn(ep->idx))
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#define ofs_UDCBCR(ep) (UDCBCRn(ep->idx))
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#define ofs_UDCDR(ep) (UDCDRn(ep->idx))
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/* Register access macros */
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#define udc_ep_readl(ep, reg) \
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__raw_readl((ep)->dev->regs + ofs_##reg(ep))
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#define udc_ep_writel(ep, reg, value) \
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__raw_writel((value), ep->dev->regs + ofs_##reg(ep))
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#define udc_ep_readb(ep, reg) \
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__raw_readb((ep)->dev->regs + ofs_##reg(ep))
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#define udc_ep_writeb(ep, reg, value) \
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__raw_writeb((value), ep->dev->regs + ofs_##reg(ep))
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#define udc_readl(dev, reg) \
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__raw_readl((dev)->regs + (reg))
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#define udc_writel(udc, reg, value) \
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__raw_writel((value), (udc)->regs + (reg))
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#define UDCCSR_MASK (UDCCSR_FST | UDCCSR_DME)
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#define UDCCISR0_EP_MASK ~0
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#define UDCCISR1_EP_MASK 0xffff
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#define UDCCSR0_CTRL_REQ_MASK (UDCCSR0_OPC | UDCCSR0_SA | UDCCSR0_RNE)
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#define EPIDX(ep) (ep->idx)
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#define EPADDR(ep) (ep->addr)
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#define EPXFERTYPE(ep) (ep->type)
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#define EPNAME(ep) (ep->name)
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#define is_ep0(ep) (!ep->idx)
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#define EPXFERTYPE_is_ISO(ep) (EPXFERTYPE(ep) == USB_ENDPOINT_XFER_ISOC)
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/*
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* Endpoint definitions
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*
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* Once enabled, pxa endpoint configuration is freezed, and cannot change
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* unless a reset happens or the udc is disabled.
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* Therefore, we must define all pxa potential endpoint definitions needed for
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* all gadget and set them up before the udc is enabled.
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*
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* As the architecture chosen is fully static, meaning the pxa endpoint
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* configurations are set up once and for all, we must provide a way to match
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* one usb endpoint (usb_ep) to several pxa endpoints. The reason is that gadget
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* layer autoconf doesn't choose the usb_ep endpoint on (config, interface, alt)
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* criteria, while the pxa architecture requires that.
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*
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* The solution is to define several pxa endpoints matching one usb_ep. Ex:
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* - "ep1-in" matches pxa endpoint EPA (which is an IN ep at addr 1, when
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* the udc talks on (config=3, interface=0, alt=0)
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* - "ep1-in" matches pxa endpoint EPB (which is an IN ep at addr 1, when
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* the udc talks on (config=3, interface=0, alt=1)
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* - "ep1-in" matches pxa endpoint EPC (which is an IN ep at addr 1, when
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* the udc talks on (config=2, interface=0, alt=0)
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*
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* We'll define the pxa endpoint by its index (EPA => idx=1, EPB => idx=2, ...)
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*/
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/*
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* Endpoint definition helpers
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*/
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#define USB_EP_DEF(addr, bname, dir, type, maxpkt) \
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{ .usb_ep = { .name = bname, .ops = &pxa_ep_ops, .maxpacket = maxpkt, }, \
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.desc = { .bEndpointAddress = addr | (dir ? USB_DIR_IN : 0), \
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.bmAttributes = type, \
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.wMaxPacketSize = maxpkt, }, \
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.dev = &memory \
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}
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#define USB_EP_BULK(addr, bname, dir) \
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USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE)
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#define USB_EP_ISO(addr, bname, dir) \
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USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE)
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#define USB_EP_INT(addr, bname, dir) \
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USB_EP_DEF(addr, bname, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE)
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#define USB_EP_IN_BULK(n) USB_EP_BULK(n, "ep" #n "in-bulk", 1)
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#define USB_EP_OUT_BULK(n) USB_EP_BULK(n, "ep" #n "out-bulk", 0)
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#define USB_EP_IN_ISO(n) USB_EP_ISO(n, "ep" #n "in-iso", 1)
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#define USB_EP_OUT_ISO(n) USB_EP_ISO(n, "ep" #n "out-iso", 0)
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#define USB_EP_IN_INT(n) USB_EP_INT(n, "ep" #n "in-int", 1)
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#define USB_EP_CTRL USB_EP_DEF(0, "ep0", 0, 0, EP0_FIFO_SIZE)
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#define PXA_EP_DEF(_idx, _addr, dir, _type, maxpkt, _config, iface, altset) \
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{ \
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.dev = &memory, \
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.name = "ep" #_idx, \
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.idx = _idx, .enabled = 0, \
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.dir_in = dir, .addr = _addr, \
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.config = _config, .interface = iface, .alternate = altset, \
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.type = _type, .fifo_size = maxpkt, \
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}
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#define PXA_EP_BULK(_idx, addr, dir, config, iface, alt) \
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PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_BULK, BULK_FIFO_SIZE, \
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config, iface, alt)
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#define PXA_EP_ISO(_idx, addr, dir, config, iface, alt) \
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PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_ISOC, ISO_FIFO_SIZE, \
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config, iface, alt)
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#define PXA_EP_INT(_idx, addr, dir, config, iface, alt) \
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PXA_EP_DEF(_idx, addr, dir, USB_ENDPOINT_XFER_INT, INT_FIFO_SIZE, \
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config, iface, alt)
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#define PXA_EP_IN_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 1, c, f, a)
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#define PXA_EP_OUT_BULK(i, adr, c, f, a) PXA_EP_BULK(i, adr, 0, c, f, a)
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#define PXA_EP_IN_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 1, c, f, a)
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#define PXA_EP_OUT_ISO(i, adr, c, f, a) PXA_EP_ISO(i, adr, 0, c, f, a)
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#define PXA_EP_IN_INT(i, adr, c, f, a) PXA_EP_INT(i, adr, 1, c, f, a)
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#define PXA_EP_CTRL PXA_EP_DEF(0, 0, 0, 0, EP0_FIFO_SIZE, 0, 0, 0)
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struct pxa27x_udc;
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struct stats {
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unsigned long in_ops;
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unsigned long out_ops;
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unsigned long in_bytes;
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unsigned long out_bytes;
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unsigned long irqs;
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};
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/**
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* struct udc_usb_ep - container of each usb_ep structure
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* @usb_ep: usb endpoint
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* @desc: usb descriptor, especially type and address
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* @dev: udc managing this endpoint
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* @pxa_ep: matching pxa_ep (cache of find_pxa_ep() call)
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*/
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struct udc_usb_ep {
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struct usb_ep usb_ep;
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struct usb_endpoint_descriptor desc;
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struct pxa_udc *dev;
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struct pxa_ep *pxa_ep;
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};
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/**
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* struct pxa_ep - pxa endpoint
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* @dev: udc device
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* @queue: requests queue
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* @lock: lock to pxa_ep data (queues and stats)
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* @enabled: true when endpoint enabled (not stopped by gadget layer)
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* @in_handle_ep: number of recursions of handle_ep() function
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* Prevents deadlocks or infinite recursions of types :
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* irq->handle_ep()->req_done()->req.complete()->pxa_ep_queue()->handle_ep()
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* or
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* pxa_ep_queue()->handle_ep()->req_done()->req.complete()->pxa_ep_queue()
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* @idx: endpoint index (1 => epA, 2 => epB, ..., 24 => epX)
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* @name: endpoint name (for trace/debug purpose)
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* @dir_in: 1 if IN endpoint, 0 if OUT endpoint
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* @addr: usb endpoint number
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* @config: configuration in which this endpoint is active
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* @interface: interface in which this endpoint is active
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* @alternate: altsetting in which this endpoitn is active
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* @fifo_size: max packet size in the endpoint fifo
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* @type: endpoint type (bulk, iso, int, ...)
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* @udccsr_value: save register of UDCCSR0 for suspend/resume
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* @udccr_value: save register of UDCCR for suspend/resume
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* @stats: endpoint statistics
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*
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* The *PROBLEM* is that pxa's endpoint configuration scheme is both misdesigned
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* (cares about config/interface/altsetting, thus placing needless limits on
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* device capability) and full of implementation bugs forcing it to be set up
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* for use more or less like a pxa255.
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*
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* As we define the pxa_ep statically, we must guess all needed pxa_ep for all
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* gadget which may work with this udc driver.
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*/
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struct pxa_ep {
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struct pxa_udc *dev;
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struct list_head queue;
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spinlock_t lock; /* Protects this structure */
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/* (queues, stats) */
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unsigned enabled:1;
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unsigned in_handle_ep:1;
|
|
|
|
unsigned idx:5;
|
|
char *name;
|
|
|
|
/*
|
|
* Specific pxa endpoint data, needed for hardware initialization
|
|
*/
|
|
unsigned dir_in:1;
|
|
unsigned addr:4;
|
|
unsigned config:2;
|
|
unsigned interface:3;
|
|
unsigned alternate:3;
|
|
unsigned fifo_size;
|
|
unsigned type;
|
|
|
|
#ifdef CONFIG_PM
|
|
u32 udccsr_value;
|
|
u32 udccr_value;
|
|
#endif
|
|
struct stats stats;
|
|
};
|
|
|
|
/**
|
|
* struct pxa27x_request - container of each usb_request structure
|
|
* @req: usb request
|
|
* @udc_usb_ep: usb endpoint the request was submitted on
|
|
* @in_use: sanity check if request already queued on an pxa_ep
|
|
* @queue: linked list of requests, linked on pxa_ep->queue
|
|
*/
|
|
struct pxa27x_request {
|
|
struct usb_request req;
|
|
struct udc_usb_ep *udc_usb_ep;
|
|
unsigned in_use:1;
|
|
struct list_head queue;
|
|
};
|
|
|
|
enum ep0_state {
|
|
WAIT_FOR_SETUP,
|
|
SETUP_STAGE,
|
|
IN_DATA_STAGE,
|
|
OUT_DATA_STAGE,
|
|
IN_STATUS_STAGE,
|
|
OUT_STATUS_STAGE,
|
|
STALL,
|
|
WAIT_ACK_SET_CONF_INTERF
|
|
};
|
|
|
|
static char *ep0_state_name[] = {
|
|
"WAIT_FOR_SETUP", "SETUP_STAGE", "IN_DATA_STAGE", "OUT_DATA_STAGE",
|
|
"IN_STATUS_STAGE", "OUT_STATUS_STAGE", "STALL",
|
|
"WAIT_ACK_SET_CONF_INTERF"
|
|
};
|
|
#define EP0_STNAME(udc) ep0_state_name[(udc)->ep0state]
|
|
|
|
#define EP0_FIFO_SIZE 16U
|
|
#define BULK_FIFO_SIZE 64U
|
|
#define ISO_FIFO_SIZE 256U
|
|
#define INT_FIFO_SIZE 16U
|
|
|
|
struct udc_stats {
|
|
unsigned long irqs_reset;
|
|
unsigned long irqs_suspend;
|
|
unsigned long irqs_resume;
|
|
unsigned long irqs_reconfig;
|
|
};
|
|
|
|
#define NR_USB_ENDPOINTS (1 + 5) /* ep0 + ep1in-bulk + .. + ep3in-iso */
|
|
#define NR_PXA_ENDPOINTS (1 + 14) /* ep0 + epA + epB + .. + epX */
|
|
|
|
/**
|
|
* struct pxa_udc - udc structure
|
|
* @regs: mapped IO space
|
|
* @irq: udc irq
|
|
* @clk: udc clock
|
|
* @usb_gadget: udc gadget structure
|
|
* @driver: bound gadget (zero, g_ether, g_mass_storage, ...)
|
|
* @dev: device
|
|
* @mach: machine info, used to activate specific GPIO
|
|
* @transceiver: external transceiver to handle vbus sense and D+ pullup
|
|
* @ep0state: control endpoint state machine state
|
|
* @stats: statistics on udc usage
|
|
* @udc_usb_ep: array of usb endpoints offered by the gadget
|
|
* @pxa_ep: array of pxa available endpoints
|
|
* @enabled: UDC was enabled by a previous udc_enable()
|
|
* @pullup_on: if pullup resistor connected to D+ pin
|
|
* @pullup_resume: if pullup resistor should be connected to D+ pin on resume
|
|
* @config: UDC active configuration
|
|
* @last_interface: UDC interface of the last SET_INTERFACE host request
|
|
* @last_alternate: UDC altsetting of the last SET_INTERFACE host request
|
|
* @udccsr0: save of udccsr0 in case of suspend
|
|
* @debugfs_root: root entry of debug filesystem
|
|
* @debugfs_state: debugfs entry for "udcstate"
|
|
* @debugfs_queues: debugfs entry for "queues"
|
|
* @debugfs_eps: debugfs entry for "epstate"
|
|
*/
|
|
struct pxa_udc {
|
|
void __iomem *regs;
|
|
int irq;
|
|
struct clk *clk;
|
|
|
|
struct usb_gadget gadget;
|
|
struct usb_gadget_driver *driver;
|
|
struct device *dev;
|
|
struct pxa2xx_udc_mach_info *mach;
|
|
struct usb_phy *transceiver;
|
|
|
|
enum ep0_state ep0state;
|
|
struct udc_stats stats;
|
|
|
|
struct udc_usb_ep udc_usb_ep[NR_USB_ENDPOINTS];
|
|
struct pxa_ep pxa_ep[NR_PXA_ENDPOINTS];
|
|
|
|
unsigned enabled:1;
|
|
unsigned pullup_on:1;
|
|
unsigned pullup_resume:1;
|
|
unsigned vbus_sensed:1;
|
|
unsigned config:2;
|
|
unsigned last_interface:3;
|
|
unsigned last_alternate:3;
|
|
|
|
#ifdef CONFIG_PM
|
|
unsigned udccsr0;
|
|
#endif
|
|
#ifdef CONFIG_USB_GADGET_DEBUG_FS
|
|
struct dentry *debugfs_root;
|
|
struct dentry *debugfs_state;
|
|
struct dentry *debugfs_queues;
|
|
struct dentry *debugfs_eps;
|
|
#endif
|
|
};
|
|
|
|
static inline struct pxa_udc *to_gadget_udc(struct usb_gadget *gadget)
|
|
{
|
|
return container_of(gadget, struct pxa_udc, gadget);
|
|
}
|
|
|
|
/*
|
|
* Debugging/message support
|
|
*/
|
|
#define ep_dbg(ep, fmt, arg...) \
|
|
dev_dbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
|
|
#define ep_vdbg(ep, fmt, arg...) \
|
|
dev_vdbg(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
|
|
#define ep_err(ep, fmt, arg...) \
|
|
dev_err(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
|
|
#define ep_info(ep, fmt, arg...) \
|
|
dev_info(ep->dev->dev, "%s:%s: " fmt, EPNAME(ep), __func__, ## arg)
|
|
#define ep_warn(ep, fmt, arg...) \
|
|
dev_warn(ep->dev->dev, "%s:%s:" fmt, EPNAME(ep), __func__, ## arg)
|
|
|
|
#endif /* __LINUX_USB_GADGET_PXA27X_H */
|