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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d052d1beff
Convert everyone who uses platform_bus_type to include linux/platform_device.h. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Greg Kroah-Hartman <gregkh@suse.de>
177 lines
4.9 KiB
C
177 lines
4.9 KiB
C
/*
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* SGI O2 MACE PS2 controller driver for linux
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*
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* Copyright (C) 2002 Vivien Chappelier
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/serio.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/delay.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include <linux/err.h>
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#include <asm/io.h>
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#include <asm/irq.h>
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#include <asm/system.h>
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#include <asm/ip32/mace.h>
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#include <asm/ip32/ip32_ints.h>
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MODULE_AUTHOR("Vivien Chappelier <vivien.chappelier@linux-mips.org");
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MODULE_DESCRIPTION("SGI O2 MACE PS2 controller driver");
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MODULE_LICENSE("GPL");
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#define MACE_PS2_TIMEOUT 10000 /* in 50us unit */
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#define PS2_STATUS_CLOCK_SIGNAL BIT(0) /* external clock signal */
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#define PS2_STATUS_CLOCK_INHIBIT BIT(1) /* clken output signal */
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#define PS2_STATUS_TX_INPROGRESS BIT(2) /* transmission in progress */
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#define PS2_STATUS_TX_EMPTY BIT(3) /* empty transmit buffer */
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#define PS2_STATUS_RX_FULL BIT(4) /* full receive buffer */
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#define PS2_STATUS_RX_INPROGRESS BIT(5) /* reception in progress */
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#define PS2_STATUS_ERROR_PARITY BIT(6) /* parity error */
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#define PS2_STATUS_ERROR_FRAMING BIT(7) /* framing error */
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#define PS2_CONTROL_TX_CLOCK_DISABLE BIT(0) /* inhibit clock signal after TX */
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#define PS2_CONTROL_TX_ENABLE BIT(1) /* transmit enable */
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#define PS2_CONTROL_TX_INT_ENABLE BIT(2) /* enable transmit interrupt */
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#define PS2_CONTROL_RX_INT_ENABLE BIT(3) /* enable receive interrupt */
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#define PS2_CONTROL_RX_CLOCK_ENABLE BIT(4) /* pause reception if set to 0 */
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#define PS2_CONTROL_RESET BIT(5) /* reset */
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struct maceps2_data {
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struct mace_ps2port *port;
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int irq;
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};
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static struct maceps2_data port_data[2];
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static struct serio *maceps2_port[2];
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static struct platform_device *maceps2_device;
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static int maceps2_write(struct serio *dev, unsigned char val)
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{
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struct mace_ps2port *port = ((struct maceps2_data *)dev->port_data)->port;
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unsigned int timeout = MACE_PS2_TIMEOUT;
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do {
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if (port->status & PS2_STATUS_TX_EMPTY) {
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port->tx = val;
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return 0;
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}
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udelay(50);
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} while (timeout--);
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return -1;
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}
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static irqreturn_t maceps2_interrupt(int irq, void *dev_id,
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struct pt_regs *regs)
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{
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struct serio *dev = dev_id;
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struct mace_ps2port *port = ((struct maceps2_data *)dev->port_data)->port;
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unsigned long byte;
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if (port->status & PS2_STATUS_RX_FULL) {
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byte = port->rx;
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serio_interrupt(dev, byte & 0xff, 0, regs);
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}
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return IRQ_HANDLED;
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}
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static int maceps2_open(struct serio *dev)
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{
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struct maceps2_data *data = (struct maceps2_data *)dev->port_data;
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if (request_irq(data->irq, maceps2_interrupt, 0, "PS2 port", dev)) {
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printk(KERN_ERR "Could not allocate PS/2 IRQ\n");
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return -EBUSY;
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}
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/* Reset port */
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data->port->control = PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET;
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udelay(100);
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/* Enable interrupts */
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data->port->control = PS2_CONTROL_RX_CLOCK_ENABLE |
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PS2_CONTROL_TX_ENABLE |
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PS2_CONTROL_RX_INT_ENABLE;
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return 0;
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}
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static void maceps2_close(struct serio *dev)
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{
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struct maceps2_data *data = (struct maceps2_data *)dev->port_data;
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data->port->control = PS2_CONTROL_TX_CLOCK_DISABLE | PS2_CONTROL_RESET;
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udelay(100);
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free_irq(data->irq, dev);
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}
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static struct serio * __init maceps2_allocate_port(int idx)
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{
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struct serio *serio;
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serio = kmalloc(sizeof(struct serio), GFP_KERNEL);
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if (serio) {
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memset(serio, 0, sizeof(struct serio));
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serio->id.type = SERIO_8042;
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serio->write = maceps2_write;
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serio->open = maceps2_open;
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serio->close = maceps2_close;
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snprintf(serio->name, sizeof(serio->name), "MACE PS/2 port%d", idx);
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snprintf(serio->phys, sizeof(serio->phys), "mace/serio%d", idx);
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serio->port_data = &port_data[idx];
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serio->dev.parent = &maceps2_device->dev;
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}
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return serio;
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}
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static int __init maceps2_init(void)
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{
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maceps2_device = platform_device_register_simple("maceps2", -1, NULL, 0);
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if (IS_ERR(maceps2_device))
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return PTR_ERR(maceps2_device);
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port_data[0].port = &mace->perif.ps2.keyb;
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port_data[0].irq = MACEISA_KEYB_IRQ;
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port_data[1].port = &mace->perif.ps2.mouse;
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port_data[1].irq = MACEISA_MOUSE_IRQ;
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maceps2_port[0] = maceps2_allocate_port(0);
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maceps2_port[1] = maceps2_allocate_port(1);
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if (!maceps2_port[0] || !maceps2_port[1]) {
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kfree(maceps2_port[0]);
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kfree(maceps2_port[1]);
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platform_device_unregister(maceps2_device);
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return -ENOMEM;
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}
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serio_register_port(maceps2_port[0]);
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serio_register_port(maceps2_port[1]);
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return 0;
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}
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static void __exit maceps2_exit(void)
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{
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serio_unregister_port(maceps2_port[0]);
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serio_unregister_port(maceps2_port[1]);
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platform_device_unregister(maceps2_device);
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}
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module_init(maceps2_init);
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module_exit(maceps2_exit);
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