mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 07:46:44 +07:00
a355020af4
The XGXS block may not get a link immediately in XGXS or XAUI loopback modes, so we still need to check it. Split falcon_xaui_link_ok() into falcon_xgxs_link_ok(), which checks only the Falcon XGXS block, and falcon_xmac_link_ok(), which checks one or both sides of the link as appropriate. Also rename falcon_check_xaui_link() to falcon_xmac_link_ok_retry(). Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: David S. Miller <davem@davemloft.net>
375 lines
12 KiB
C
375 lines
12 KiB
C
/****************************************************************************
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* Driver for Solarflare Solarstorm network controllers and boards
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* Copyright 2005-2006 Fen Systems Ltd.
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* Copyright 2006-2009 Solarflare Communications Inc.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation, incorporated herein by reference.
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*/
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#include <linux/delay.h>
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#include "net_driver.h"
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#include "efx.h"
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#include "nic.h"
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#include "regs.h"
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#include "io.h"
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#include "mac.h"
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#include "mdio_10g.h"
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#include "phy.h"
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#include "workarounds.h"
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/**************************************************************************
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*
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* MAC operations
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*
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*************************************************************************/
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/* Configure the XAUI driver that is an output from Falcon */
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static void falcon_setup_xaui(struct efx_nic *efx)
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{
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efx_oword_t sdctl, txdrv;
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/* Move the XAUI into low power, unless there is no PHY, in
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* which case the XAUI will have to drive a cable. */
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if (efx->phy_type == PHY_TYPE_NONE)
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return;
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efx_reado(efx, &sdctl, FR_AB_XX_SD_CTL);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVD, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVC, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVB, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_HIDRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
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EFX_SET_OWORD_FIELD(sdctl, FRF_AB_XX_LODRVA, FFE_AB_XX_SD_CTL_DRV_DEF);
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efx_writeo(efx, &sdctl, FR_AB_XX_SD_CTL);
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EFX_POPULATE_OWORD_8(txdrv,
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FRF_AB_XX_DEQD, FFE_AB_XX_TXDRV_DEQ_DEF,
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FRF_AB_XX_DEQC, FFE_AB_XX_TXDRV_DEQ_DEF,
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FRF_AB_XX_DEQB, FFE_AB_XX_TXDRV_DEQ_DEF,
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FRF_AB_XX_DEQA, FFE_AB_XX_TXDRV_DEQ_DEF,
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FRF_AB_XX_DTXD, FFE_AB_XX_TXDRV_DTX_DEF,
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FRF_AB_XX_DTXC, FFE_AB_XX_TXDRV_DTX_DEF,
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FRF_AB_XX_DTXB, FFE_AB_XX_TXDRV_DTX_DEF,
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FRF_AB_XX_DTXA, FFE_AB_XX_TXDRV_DTX_DEF);
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efx_writeo(efx, &txdrv, FR_AB_XX_TXDRV_CTL);
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}
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int falcon_reset_xaui(struct efx_nic *efx)
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{
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struct falcon_nic_data *nic_data = efx->nic_data;
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efx_oword_t reg;
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int count;
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/* Don't fetch MAC statistics over an XMAC reset */
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WARN_ON(nic_data->stats_disable_count == 0);
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/* Start reset sequence */
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EFX_POPULATE_OWORD_1(reg, FRF_AB_XX_RST_XX_EN, 1);
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efx_writeo(efx, ®, FR_AB_XX_PWR_RST);
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/* Wait up to 10 ms for completion, then reinitialise */
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for (count = 0; count < 1000; count++) {
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efx_reado(efx, ®, FR_AB_XX_PWR_RST);
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if (EFX_OWORD_FIELD(reg, FRF_AB_XX_RST_XX_EN) == 0 &&
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EFX_OWORD_FIELD(reg, FRF_AB_XX_SD_RST_ACT) == 0) {
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falcon_setup_xaui(efx);
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return 0;
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}
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udelay(10);
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}
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EFX_ERR(efx, "timed out waiting for XAUI/XGXS reset\n");
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return -ETIMEDOUT;
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}
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static void falcon_mask_status_intr(struct efx_nic *efx, bool enable)
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{
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efx_oword_t reg;
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if ((efx_nic_rev(efx) != EFX_REV_FALCON_B0) || LOOPBACK_INTERNAL(efx))
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return;
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/* We expect xgmii faults if the wireside link is up */
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if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up)
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return;
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/* We can only use this interrupt to signal the negative edge of
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* xaui_align [we have to poll the positive edge]. */
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if (efx->xmac_poll_required)
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return;
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/* Flush the ISR */
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if (enable)
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efx_reado(efx, ®, FR_AB_XM_MGT_INT_MSK);
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EFX_POPULATE_OWORD_2(reg,
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FRF_AB_XM_MSK_RMTFLT, !enable,
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FRF_AB_XM_MSK_LCLFLT, !enable);
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efx_writeo(efx, ®, FR_AB_XM_MGT_INT_MASK);
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}
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static bool falcon_xgxs_link_ok(struct efx_nic *efx)
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{
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efx_oword_t reg;
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bool align_done, link_ok = false;
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int sync_status;
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/* Read link status */
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efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
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align_done = EFX_OWORD_FIELD(reg, FRF_AB_XX_ALIGN_DONE);
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sync_status = EFX_OWORD_FIELD(reg, FRF_AB_XX_SYNC_STAT);
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if (align_done && (sync_status == FFE_AB_XX_STAT_ALL_LANES))
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link_ok = true;
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/* Clear link status ready for next read */
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_COMMA_DET, FFE_AB_XX_STAT_ALL_LANES);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_CHAR_ERR, FFE_AB_XX_STAT_ALL_LANES);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_DISPERR, FFE_AB_XX_STAT_ALL_LANES);
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efx_writeo(efx, ®, FR_AB_XX_CORE_STAT);
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return link_ok;
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}
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static bool falcon_xmac_link_ok(struct efx_nic *efx)
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{
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/*
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* Check MAC's XGXS link status except when using XGMII loopback
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* which bypasses the XGXS block.
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* If possible, check PHY's XGXS link status except when using
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* MAC loopback.
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*/
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return (efx->loopback_mode == LOOPBACK_XGMII ||
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falcon_xgxs_link_ok(efx)) &&
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(!(efx->mdio.mmds & (1 << MDIO_MMD_PHYXS)) ||
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LOOPBACK_INTERNAL(efx) ||
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efx_mdio_phyxgxs_lane_sync(efx));
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}
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void falcon_reconfigure_xmac_core(struct efx_nic *efx)
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{
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unsigned int max_frame_len;
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efx_oword_t reg;
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bool rx_fc = !!(efx->link_state.fc & EFX_FC_RX);
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bool tx_fc = !!(efx->link_state.fc & EFX_FC_TX);
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/* Configure MAC - cut-thru mode is hard wired on */
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EFX_POPULATE_OWORD_3(reg,
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FRF_AB_XM_RX_JUMBO_MODE, 1,
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FRF_AB_XM_TX_STAT_EN, 1,
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FRF_AB_XM_RX_STAT_EN, 1);
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efx_writeo(efx, ®, FR_AB_XM_GLB_CFG);
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/* Configure TX */
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EFX_POPULATE_OWORD_6(reg,
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FRF_AB_XM_TXEN, 1,
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FRF_AB_XM_TX_PRMBL, 1,
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FRF_AB_XM_AUTO_PAD, 1,
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FRF_AB_XM_TXCRC, 1,
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FRF_AB_XM_FCNTL, tx_fc,
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FRF_AB_XM_IPG, 0x3);
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efx_writeo(efx, ®, FR_AB_XM_TX_CFG);
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/* Configure RX */
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EFX_POPULATE_OWORD_5(reg,
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FRF_AB_XM_RXEN, 1,
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FRF_AB_XM_AUTO_DEPAD, 0,
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FRF_AB_XM_ACPT_ALL_MCAST, 1,
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FRF_AB_XM_ACPT_ALL_UCAST, efx->promiscuous,
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FRF_AB_XM_PASS_CRC_ERR, 1);
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efx_writeo(efx, ®, FR_AB_XM_RX_CFG);
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/* Set frame length */
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max_frame_len = EFX_MAX_FRAME_LEN(efx->net_dev->mtu);
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EFX_POPULATE_OWORD_1(reg, FRF_AB_XM_MAX_RX_FRM_SIZE, max_frame_len);
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efx_writeo(efx, ®, FR_AB_XM_RX_PARAM);
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EFX_POPULATE_OWORD_2(reg,
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FRF_AB_XM_MAX_TX_FRM_SIZE, max_frame_len,
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FRF_AB_XM_TX_JUMBO_MODE, 1);
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efx_writeo(efx, ®, FR_AB_XM_TX_PARAM);
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EFX_POPULATE_OWORD_2(reg,
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FRF_AB_XM_PAUSE_TIME, 0xfffe, /* MAX PAUSE TIME */
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FRF_AB_XM_DIS_FCNTL, !rx_fc);
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efx_writeo(efx, ®, FR_AB_XM_FC);
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/* Set MAC address */
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memcpy(®, &efx->net_dev->dev_addr[0], 4);
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efx_writeo(efx, ®, FR_AB_XM_ADR_LO);
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memcpy(®, &efx->net_dev->dev_addr[4], 2);
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efx_writeo(efx, ®, FR_AB_XM_ADR_HI);
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}
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static void falcon_reconfigure_xgxs_core(struct efx_nic *efx)
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{
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efx_oword_t reg;
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bool xgxs_loopback = (efx->loopback_mode == LOOPBACK_XGXS);
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bool xaui_loopback = (efx->loopback_mode == LOOPBACK_XAUI);
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bool xgmii_loopback = (efx->loopback_mode == LOOPBACK_XGMII);
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/* XGXS block is flaky and will need to be reset if moving
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* into our out of XGMII, XGXS or XAUI loopbacks. */
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if (EFX_WORKAROUND_5147(efx)) {
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bool old_xgmii_loopback, old_xgxs_loopback, old_xaui_loopback;
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bool reset_xgxs;
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efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
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old_xgxs_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN);
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old_xgmii_loopback =
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EFX_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN);
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efx_reado(efx, ®, FR_AB_XX_SD_CTL);
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old_xaui_loopback = EFX_OWORD_FIELD(reg, FRF_AB_XX_LPBKA);
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/* The PHY driver may have turned XAUI off */
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reset_xgxs = ((xgxs_loopback != old_xgxs_loopback) ||
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(xaui_loopback != old_xaui_loopback) ||
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(xgmii_loopback != old_xgmii_loopback));
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if (reset_xgxs)
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falcon_reset_xaui(efx);
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}
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efx_reado(efx, ®, FR_AB_XX_CORE_STAT);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_FORCE_SIG,
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(xgxs_loopback || xaui_loopback) ?
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FFE_AB_XX_FORCE_SIG_ALL_LANES : 0);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGXS_LB_EN, xgxs_loopback);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_XGMII_LB_EN, xgmii_loopback);
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efx_writeo(efx, ®, FR_AB_XX_CORE_STAT);
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efx_reado(efx, ®, FR_AB_XX_SD_CTL);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKD, xaui_loopback);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKC, xaui_loopback);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKB, xaui_loopback);
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EFX_SET_OWORD_FIELD(reg, FRF_AB_XX_LPBKA, xaui_loopback);
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efx_writeo(efx, ®, FR_AB_XX_SD_CTL);
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}
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/* Try to bring up the Falcon side of the Falcon-Phy XAUI link */
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static bool falcon_xmac_link_ok_retry(struct efx_nic *efx, int tries)
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{
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bool mac_up = falcon_xmac_link_ok(efx);
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if (LOOPBACK_MASK(efx) & LOOPBACKS_EXTERNAL(efx) & LOOPBACKS_WS ||
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efx_phy_mode_disabled(efx->phy_mode))
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/* XAUI link is expected to be down */
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return mac_up;
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falcon_stop_nic_stats(efx);
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while (!mac_up && tries) {
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EFX_LOG(efx, "bashing xaui\n");
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falcon_reset_xaui(efx);
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udelay(200);
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mac_up = falcon_xmac_link_ok(efx);
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--tries;
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}
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falcon_start_nic_stats(efx);
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return mac_up;
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}
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static bool falcon_xmac_check_fault(struct efx_nic *efx)
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{
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return !falcon_xmac_link_ok_retry(efx, 5);
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}
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static int falcon_reconfigure_xmac(struct efx_nic *efx)
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{
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falcon_mask_status_intr(efx, false);
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falcon_reconfigure_xgxs_core(efx);
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falcon_reconfigure_xmac_core(efx);
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falcon_reconfigure_mac_wrapper(efx);
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efx->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 5);
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falcon_mask_status_intr(efx, true);
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return 0;
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}
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static void falcon_update_stats_xmac(struct efx_nic *efx)
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{
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struct efx_mac_stats *mac_stats = &efx->mac_stats;
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/* Update MAC stats from DMAed values */
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FALCON_STAT(efx, XgRxOctets, rx_bytes);
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FALCON_STAT(efx, XgRxOctetsOK, rx_good_bytes);
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FALCON_STAT(efx, XgRxPkts, rx_packets);
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FALCON_STAT(efx, XgRxPktsOK, rx_good);
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FALCON_STAT(efx, XgRxBroadcastPkts, rx_broadcast);
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FALCON_STAT(efx, XgRxMulticastPkts, rx_multicast);
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FALCON_STAT(efx, XgRxUnicastPkts, rx_unicast);
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FALCON_STAT(efx, XgRxUndersizePkts, rx_lt64);
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FALCON_STAT(efx, XgRxOversizePkts, rx_gtjumbo);
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FALCON_STAT(efx, XgRxJabberPkts, rx_bad_gtjumbo);
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FALCON_STAT(efx, XgRxUndersizeFCSerrorPkts, rx_bad_lt64);
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FALCON_STAT(efx, XgRxDropEvents, rx_overflow);
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FALCON_STAT(efx, XgRxFCSerrorPkts, rx_bad);
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FALCON_STAT(efx, XgRxAlignError, rx_align_error);
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FALCON_STAT(efx, XgRxSymbolError, rx_symbol_error);
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FALCON_STAT(efx, XgRxInternalMACError, rx_internal_error);
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FALCON_STAT(efx, XgRxControlPkts, rx_control);
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FALCON_STAT(efx, XgRxPausePkts, rx_pause);
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FALCON_STAT(efx, XgRxPkts64Octets, rx_64);
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FALCON_STAT(efx, XgRxPkts65to127Octets, rx_65_to_127);
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FALCON_STAT(efx, XgRxPkts128to255Octets, rx_128_to_255);
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FALCON_STAT(efx, XgRxPkts256to511Octets, rx_256_to_511);
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FALCON_STAT(efx, XgRxPkts512to1023Octets, rx_512_to_1023);
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FALCON_STAT(efx, XgRxPkts1024to15xxOctets, rx_1024_to_15xx);
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FALCON_STAT(efx, XgRxPkts15xxtoMaxOctets, rx_15xx_to_jumbo);
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FALCON_STAT(efx, XgRxLengthError, rx_length_error);
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FALCON_STAT(efx, XgTxPkts, tx_packets);
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FALCON_STAT(efx, XgTxOctets, tx_bytes);
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FALCON_STAT(efx, XgTxMulticastPkts, tx_multicast);
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FALCON_STAT(efx, XgTxBroadcastPkts, tx_broadcast);
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FALCON_STAT(efx, XgTxUnicastPkts, tx_unicast);
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FALCON_STAT(efx, XgTxControlPkts, tx_control);
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FALCON_STAT(efx, XgTxPausePkts, tx_pause);
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FALCON_STAT(efx, XgTxPkts64Octets, tx_64);
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FALCON_STAT(efx, XgTxPkts65to127Octets, tx_65_to_127);
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FALCON_STAT(efx, XgTxPkts128to255Octets, tx_128_to_255);
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FALCON_STAT(efx, XgTxPkts256to511Octets, tx_256_to_511);
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FALCON_STAT(efx, XgTxPkts512to1023Octets, tx_512_to_1023);
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FALCON_STAT(efx, XgTxPkts1024to15xxOctets, tx_1024_to_15xx);
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FALCON_STAT(efx, XgTxPkts1519toMaxOctets, tx_15xx_to_jumbo);
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FALCON_STAT(efx, XgTxUndersizePkts, tx_lt64);
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FALCON_STAT(efx, XgTxOversizePkts, tx_gtjumbo);
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FALCON_STAT(efx, XgTxNonTcpUdpPkt, tx_non_tcpudp);
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FALCON_STAT(efx, XgTxMacSrcErrPkt, tx_mac_src_error);
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FALCON_STAT(efx, XgTxIpSrcErrPkt, tx_ip_src_error);
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/* Update derived statistics */
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mac_stats->tx_good_bytes =
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(mac_stats->tx_bytes - mac_stats->tx_bad_bytes -
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mac_stats->tx_control * 64);
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mac_stats->rx_bad_bytes =
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(mac_stats->rx_bytes - mac_stats->rx_good_bytes -
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mac_stats->rx_control * 64);
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}
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void falcon_poll_xmac(struct efx_nic *efx)
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{
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if (!EFX_WORKAROUND_5147(efx) || !efx->link_state.up ||
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!efx->xmac_poll_required)
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|
return;
|
|
|
|
falcon_mask_status_intr(efx, false);
|
|
efx->xmac_poll_required = !falcon_xmac_link_ok_retry(efx, 1);
|
|
falcon_mask_status_intr(efx, true);
|
|
}
|
|
|
|
struct efx_mac_operations falcon_xmac_operations = {
|
|
.reconfigure = falcon_reconfigure_xmac,
|
|
.update_stats = falcon_update_stats_xmac,
|
|
.check_fault = falcon_xmac_check_fault,
|
|
};
|