Curtis Malainey ba0b3a977e ASoC: rt5677: Set ADC clock to use PLL and enable ASRC ... Use the PLL to kept the correct 24M clock rate so frequency shift does not occur when using the DSP VAD. Signed-off-by: Curtis Malainey <cujomalainey@chromium.org> Link: https://lore.kernel.org/r/20191106011335.223061-11-cujomalainey@chromium.org Signed-off-by: Mark Brown <broonie@kernel.org>		2019-11-11 13:02:06 +00:00
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atom	ASoC: intel: sst-mfld-platform-pcm: remove snd_pcm_ops	2019-10-08 13:41:52 +01:00
baytrail	ASoC: intel: sst-baytrail-pcm: remove snd_pcm_ops	2019-10-08 13:42:11 +01:00
boards	ASoC: rt5677: Set ADC clock to use PLL and enable ASRC	2019-11-11 13:02:06 +00:00
common	ASoC: Intel: Add acpi match for rt1011 based m/c driver	2019-11-04 13:22:34 +00:00
haswell	ASoC: intel: sst-haswell-pcm: remove snd_pcm_ops	2019-10-08 13:41:14 +01:00
skylake	ASoC: intel: skl-pcm: remove snd_pcm_ops	2019-10-08 13:41:33 +01:00
Kconfig	ASoC: Intel: Skylake: mark HDAudio codec support as deprecated.	2019-11-04 13:24:25 +00:00
Makefile	ASoC: Intel: Fix Kconfig with top-level selector	2018-01-08 16:18:48 +00:00