mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-24 21:00:53 +07:00
ba07975f0f
Adds two new functions, ipu_set_csi_src_mux() and ipu_set_ic_src_mux(), that select the inputs to the CSI and IC respectively. Both muxes are programmed in the IPU_CONF register. Signed-off-by: Steve Longerbeam <steve_longerbeam@mentor.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
238 lines
7.0 KiB
C
238 lines
7.0 KiB
C
/*
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* Copyright 2005-2009 Freescale Semiconductor, Inc.
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*
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* The code contained herein is licensed under the GNU Lesser General
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* Public License. You may obtain a copy of the GNU Lesser General
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* Public License Version 2.1 or later at the following locations:
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*
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* http://www.opensource.org/licenses/lgpl-license.html
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* http://www.gnu.org/copyleft/lgpl.html
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*/
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#ifndef __DRM_IPU_H__
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#define __DRM_IPU_H__
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#include <linux/types.h>
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#include <linux/videodev2.h>
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#include <linux/bitmap.h>
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#include <linux/fb.h>
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struct ipu_soc;
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enum ipuv3_type {
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IPUV3EX,
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IPUV3M,
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IPUV3H,
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};
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#define IPU_PIX_FMT_GBR24 v4l2_fourcc('G', 'B', 'R', '3')
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/*
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* Bitfield of Display Interface signal polarities.
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*/
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struct ipu_di_signal_cfg {
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unsigned datamask_en:1;
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unsigned interlaced:1;
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unsigned odd_field_first:1;
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unsigned clksel_en:1;
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unsigned clkidle_en:1;
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unsigned data_pol:1; /* true = inverted */
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unsigned clk_pol:1; /* true = rising edge */
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unsigned enable_pol:1;
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unsigned Hsync_pol:1; /* true = active high */
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unsigned Vsync_pol:1;
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u16 width;
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u16 height;
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u32 pixel_fmt;
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u16 h_start_width;
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u16 h_sync_width;
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u16 h_end_width;
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u16 v_start_width;
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u16 v_sync_width;
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u16 v_end_width;
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u32 v_to_h_sync;
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unsigned long pixelclock;
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#define IPU_DI_CLKMODE_SYNC (1 << 0)
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#define IPU_DI_CLKMODE_EXT (1 << 1)
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unsigned long clkflags;
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u8 hsync_pin;
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u8 vsync_pin;
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};
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enum ipu_color_space {
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IPUV3_COLORSPACE_RGB,
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IPUV3_COLORSPACE_YUV,
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IPUV3_COLORSPACE_UNKNOWN,
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};
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struct ipuv3_channel;
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enum ipu_channel_irq {
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IPU_IRQ_EOF = 0,
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IPU_IRQ_NFACK = 64,
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IPU_IRQ_NFB4EOF = 128,
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IPU_IRQ_EOS = 192,
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};
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int ipu_map_irq(struct ipu_soc *ipu, int irq);
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int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
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enum ipu_channel_irq irq);
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#define IPU_IRQ_DP_SF_START (448 + 2)
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#define IPU_IRQ_DP_SF_END (448 + 3)
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#define IPU_IRQ_BG_SF_END IPU_IRQ_DP_SF_END,
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#define IPU_IRQ_DC_FC_0 (448 + 8)
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#define IPU_IRQ_DC_FC_1 (448 + 9)
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#define IPU_IRQ_DC_FC_2 (448 + 10)
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#define IPU_IRQ_DC_FC_3 (448 + 11)
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#define IPU_IRQ_DC_FC_4 (448 + 12)
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#define IPU_IRQ_DC_FC_6 (448 + 13)
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#define IPU_IRQ_VSYNC_PRE_0 (448 + 14)
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#define IPU_IRQ_VSYNC_PRE_1 (448 + 15)
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/*
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* IPU Common functions
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*/
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void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2);
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void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi);
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/*
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* IPU Image DMA Controller (idmac) functions
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*/
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struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned channel);
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void ipu_idmac_put(struct ipuv3_channel *);
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int ipu_idmac_enable_channel(struct ipuv3_channel *channel);
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int ipu_idmac_disable_channel(struct ipuv3_channel *channel);
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int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms);
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void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
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bool doublebuffer);
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int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel);
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void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num);
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/*
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* IPU Channel Parameter Memory (cpmem) functions
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*/
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struct ipu_rgb {
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struct fb_bitfield red;
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struct fb_bitfield green;
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struct fb_bitfield blue;
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struct fb_bitfield transp;
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int bits_per_pixel;
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};
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struct ipu_image {
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struct v4l2_pix_format pix;
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struct v4l2_rect rect;
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dma_addr_t phys;
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};
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void ipu_cpmem_zero(struct ipuv3_channel *ch);
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void ipu_cpmem_set_resolution(struct ipuv3_channel *ch, int xres, int yres);
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void ipu_cpmem_set_stride(struct ipuv3_channel *ch, int stride);
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void ipu_cpmem_set_high_priority(struct ipuv3_channel *ch);
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void ipu_cpmem_set_buffer(struct ipuv3_channel *ch, int bufnum, dma_addr_t buf);
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void ipu_cpmem_interlaced_scan(struct ipuv3_channel *ch, int stride);
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void ipu_cpmem_set_burstsize(struct ipuv3_channel *ch, int burstsize);
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int ipu_cpmem_set_format_rgb(struct ipuv3_channel *ch,
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const struct ipu_rgb *rgb);
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int ipu_cpmem_set_format_passthrough(struct ipuv3_channel *ch, int width);
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void ipu_cpmem_set_yuv_interleaved(struct ipuv3_channel *ch, u32 pixel_format);
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void ipu_cpmem_set_yuv_planar_full(struct ipuv3_channel *ch,
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u32 pixel_format, int stride,
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int u_offset, int v_offset);
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void ipu_cpmem_set_yuv_planar(struct ipuv3_channel *ch,
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u32 pixel_format, int stride, int height);
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int ipu_cpmem_set_fmt(struct ipuv3_channel *ch, u32 drm_fourcc);
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int ipu_cpmem_set_image(struct ipuv3_channel *ch, struct ipu_image *image);
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/*
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* IPU Display Controller (dc) functions
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*/
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struct ipu_dc;
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struct ipu_di;
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struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel);
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void ipu_dc_put(struct ipu_dc *dc);
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int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
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u32 pixel_fmt, u32 width);
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void ipu_dc_enable(struct ipu_soc *ipu);
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void ipu_dc_enable_channel(struct ipu_dc *dc);
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void ipu_dc_disable_channel(struct ipu_dc *dc);
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void ipu_dc_disable(struct ipu_soc *ipu);
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/*
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* IPU Display Interface (di) functions
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*/
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struct ipu_di *ipu_di_get(struct ipu_soc *ipu, int disp);
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void ipu_di_put(struct ipu_di *);
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int ipu_di_disable(struct ipu_di *);
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int ipu_di_enable(struct ipu_di *);
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int ipu_di_get_num(struct ipu_di *);
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int ipu_di_init_sync_panel(struct ipu_di *, struct ipu_di_signal_cfg *sig);
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/*
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* IPU Display Multi FIFO Controller (dmfc) functions
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*/
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struct dmfc_channel;
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int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc);
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void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc);
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int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
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unsigned long bandwidth_mbs, int burstsize);
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void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc);
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int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width);
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struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipuv3_channel);
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void ipu_dmfc_put(struct dmfc_channel *dmfc);
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/*
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* IPU Display Processor (dp) functions
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*/
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#define IPU_DP_FLOW_SYNC_BG 0
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#define IPU_DP_FLOW_SYNC_FG 1
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#define IPU_DP_FLOW_ASYNC0_BG 2
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#define IPU_DP_FLOW_ASYNC0_FG 3
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#define IPU_DP_FLOW_ASYNC1_BG 4
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#define IPU_DP_FLOW_ASYNC1_FG 5
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struct ipu_dp *ipu_dp_get(struct ipu_soc *ipu, unsigned int flow);
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void ipu_dp_put(struct ipu_dp *);
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int ipu_dp_enable(struct ipu_soc *ipu);
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int ipu_dp_enable_channel(struct ipu_dp *dp);
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void ipu_dp_disable_channel(struct ipu_dp *dp);
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void ipu_dp_disable(struct ipu_soc *ipu);
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int ipu_dp_setup_channel(struct ipu_dp *dp,
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enum ipu_color_space in, enum ipu_color_space out);
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int ipu_dp_set_window_pos(struct ipu_dp *, u16 x_pos, u16 y_pos);
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int ipu_dp_set_global_alpha(struct ipu_dp *dp, bool enable, u8 alpha,
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bool bg_chan);
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/*
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* IPU CMOS Sensor Interface (csi) functions
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*/
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int ipu_csi_enable(struct ipu_soc *ipu, int csi);
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int ipu_csi_disable(struct ipu_soc *ipu, int csi);
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/*
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* IPU Sensor Multiple FIFO Controller (SMFC) functions
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*/
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int ipu_smfc_enable(struct ipu_soc *ipu);
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int ipu_smfc_disable(struct ipu_soc *ipu);
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int ipu_smfc_map_channel(struct ipu_soc *ipu, int channel, int csi_id, int mipi_id);
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int ipu_smfc_set_burstsize(struct ipu_soc *ipu, int channel, int burstsize);
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enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc);
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enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat);
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struct ipu_client_platformdata {
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int csi;
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int di;
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int dc;
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int dp;
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int dmfc;
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int dma[2];
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};
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#endif /* __DRM_IPU_H__ */
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