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With the old binding and driver architecture we had many issues: No way to assign eDMA channels to event queues, thus not able to tune the system by moving specific DMA channels to low/high priority servicing. We moved the cyclic channels to high priority within the code, but that was just a workaround to this issue. Memcopy was fundamentally broken: even if the driver scanned the DT/devices in the booted system for direct DMA users (which is not effective when the events are going through a crossbar) and created a map of 'used' channels, this information was not really usable. Since via dmaengien API the eDMA driver will be called with _some_ channel number, we would try to request this channel when any channel is requested for memcpy. By luck we got channel which is not used by any device most of the time so things worked, but if a device would have been using the given channel, but not requested it, the memcpy channel would have been waiting for HW event. The old code had the am33xx/am43xx DMA event router handling embedded. This should have been done in a separate driver since it is not part of the actual eDMA IP. There were no way to 'lock' PaRAM slots to be used by the DSP for example when booting with DT. In DT boot the edma node used more than one hwmod which is not a good practice and the kernel prints warning because of this. With the new bindings and the changes in the driver we can: - No regression with Legacy binding and non DT boot - DMA channels can be assigned to any TC (to set priority) - PaRAM slots can be reserved for other cores to use - Dynamic power management for CC and TCs, if only TC0 is used all other TC can be powered down for example Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
82 lines
2.6 KiB
C
82 lines
2.6 KiB
C
/*
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* TI EDMA definitions
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*
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* Copyright (C) 2006-2013 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* This EDMA3 programming framework exposes two basic kinds of resource:
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*
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* Channel Triggers transfers, usually from a hardware event but
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* also manually or by "chaining" from DMA completions.
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* Each channel is coupled to a Parameter RAM (PaRAM) slot.
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*
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* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
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* "set"), source and destination addresses, a link to a
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* next PaRAM slot (if any), options for the transfer, and
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* instructions for updating those addresses. There are
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* more than twice as many slots as event channels.
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*
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* Each PaRAM set describes a sequence of transfers, either for one large
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* buffer or for several discontiguous smaller buffers. An EDMA transfer
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* is driven only from a channel, which performs the transfers specified
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* in its PaRAM slot until there are no more transfers. When that last
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* transfer completes, the "link" field may be used to reload the channel's
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* PaRAM slot with a new transfer descriptor.
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*
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* The EDMA Channel Controller (CC) maps requests from channels into physical
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* Transfer Controller (TC) requests when the channel triggers (by hardware
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* or software events, or by chaining). The two physical DMA channels provided
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* by the TCs are thus shared by many logical channels.
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*
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* DaVinci hardware also has a "QDMA" mechanism which is not currently
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* supported through this interface. (DSP firmware uses it though.)
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*/
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#ifndef EDMA_H_
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#define EDMA_H_
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enum dma_event_q {
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EVENTQ_0 = 0,
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EVENTQ_1 = 1,
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EVENTQ_2 = 2,
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EVENTQ_3 = 3,
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EVENTQ_DEFAULT = -1
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};
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#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
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#define EDMA_CTLR(i) ((i) >> 16)
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#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
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struct edma_rsv_info {
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const s16 (*rsv_chans)[2];
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const s16 (*rsv_slots)[2];
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};
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/* platform_data for EDMA driver */
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struct edma_soc_info {
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/*
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* Default queue is expected to be a low-priority queue.
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* This way, long transfers on the default queue started
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* by the codec engine will not cause audio defects.
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*/
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enum dma_event_q default_queue;
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/* Resource reservation for other cores */
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struct edma_rsv_info *rsv;
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/* List of channels allocated for memcpy, terminated with -1 */
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s16 *memcpy_channels;
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s8 (*queue_priority_mapping)[2];
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const s16 (*xbar_chans)[2];
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};
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#endif
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