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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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14591d888e
Since the twl-core has been converted to use regmap it is no longer needed to allocate bigger buffer for data when writing to twl. CC: Grant Likely <grant.likely@secretlab.ca> CC: Alessandro Zummo <a.zummo@towertech.it> Acked-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Samuel Ortiz <sameo@linux.intel.com>
447 lines
12 KiB
C
447 lines
12 KiB
C
/*
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* twl6030-irq.c - TWL6030 irq support
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*
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* Copyright (C) 2005-2009 Texas Instruments, Inc.
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*
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* Modifications to defer interrupt handling to a kernel thread:
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* Copyright (C) 2006 MontaVista Software, Inc.
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*
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* Based on tlv320aic23.c:
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* Copyright (c) by Kai Svahn <kai.svahn@nokia.com>
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*
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* Code cleanup and modifications to IRQ handler.
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* by syed khasim <x0khasim@ti.com>
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*
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* TWL6030 specific code and IRQ handling changes by
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* Jagadeesh Bhaskar Pakaravoor <j-pakaravoor@ti.com>
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* Balaji T K <balajitk@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include <linux/init.h>
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#include <linux/export.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/kthread.h>
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#include <linux/i2c/twl.h>
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#include <linux/platform_device.h>
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#include <linux/suspend.h>
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#include <linux/of.h>
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#include <linux/irqdomain.h>
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#include "twl-core.h"
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/*
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* TWL6030 (unlike its predecessors, which had two level interrupt handling)
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* three interrupt registers INT_STS_A, INT_STS_B and INT_STS_C.
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* It exposes status bits saying who has raised an interrupt. There are
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* three mask registers that corresponds to these status registers, that
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* enables/disables these interrupts.
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*
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* We set up IRQs starting at a platform-specified base. An interrupt map table,
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* specifies mapping between interrupt number and the associated module.
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*/
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#define TWL6030_NR_IRQS 20
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static int twl6030_interrupt_mapping[24] = {
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PWR_INTR_OFFSET, /* Bit 0 PWRON */
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PWR_INTR_OFFSET, /* Bit 1 RPWRON */
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PWR_INTR_OFFSET, /* Bit 2 BAT_VLOW */
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RTC_INTR_OFFSET, /* Bit 3 RTC_ALARM */
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RTC_INTR_OFFSET, /* Bit 4 RTC_PERIOD */
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HOTDIE_INTR_OFFSET, /* Bit 5 HOT_DIE */
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SMPSLDO_INTR_OFFSET, /* Bit 6 VXXX_SHORT */
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SMPSLDO_INTR_OFFSET, /* Bit 7 VMMC_SHORT */
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SMPSLDO_INTR_OFFSET, /* Bit 8 VUSIM_SHORT */
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BATDETECT_INTR_OFFSET, /* Bit 9 BAT */
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SIMDETECT_INTR_OFFSET, /* Bit 10 SIM */
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MMCDETECT_INTR_OFFSET, /* Bit 11 MMC */
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RSV_INTR_OFFSET, /* Bit 12 Reserved */
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MADC_INTR_OFFSET, /* Bit 13 GPADC_RT_EOC */
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MADC_INTR_OFFSET, /* Bit 14 GPADC_SW_EOC */
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GASGAUGE_INTR_OFFSET, /* Bit 15 CC_AUTOCAL */
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USBOTG_INTR_OFFSET, /* Bit 16 ID_WKUP */
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USBOTG_INTR_OFFSET, /* Bit 17 VBUS_WKUP */
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USBOTG_INTR_OFFSET, /* Bit 18 ID */
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USB_PRES_INTR_OFFSET, /* Bit 19 VBUS */
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CHARGER_INTR_OFFSET, /* Bit 20 CHRG_CTRL */
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CHARGERFAULT_INTR_OFFSET, /* Bit 21 EXT_CHRG */
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CHARGERFAULT_INTR_OFFSET, /* Bit 22 INT_CHRG */
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RSV_INTR_OFFSET, /* Bit 23 Reserved */
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};
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/*----------------------------------------------------------------------*/
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static unsigned twl6030_irq_base;
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static int twl_irq;
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static bool twl_irq_wake_enabled;
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static struct completion irq_event;
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static atomic_t twl6030_wakeirqs = ATOMIC_INIT(0);
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static int twl6030_irq_pm_notifier(struct notifier_block *notifier,
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unsigned long pm_event, void *unused)
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{
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int chained_wakeups;
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switch (pm_event) {
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case PM_SUSPEND_PREPARE:
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chained_wakeups = atomic_read(&twl6030_wakeirqs);
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if (chained_wakeups && !twl_irq_wake_enabled) {
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if (enable_irq_wake(twl_irq))
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pr_err("twl6030 IRQ wake enable failed\n");
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else
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twl_irq_wake_enabled = true;
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} else if (!chained_wakeups && twl_irq_wake_enabled) {
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disable_irq_wake(twl_irq);
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twl_irq_wake_enabled = false;
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}
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disable_irq(twl_irq);
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break;
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case PM_POST_SUSPEND:
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enable_irq(twl_irq);
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break;
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default:
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break;
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}
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return NOTIFY_DONE;
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}
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static struct notifier_block twl6030_irq_pm_notifier_block = {
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.notifier_call = twl6030_irq_pm_notifier,
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};
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/*
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* This thread processes interrupts reported by the Primary Interrupt Handler.
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*/
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static int twl6030_irq_thread(void *data)
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{
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long irq = (long)data;
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static unsigned i2c_errors;
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static const unsigned max_i2c_errors = 100;
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int ret;
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while (!kthread_should_stop()) {
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int i;
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union {
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u8 bytes[4];
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u32 int_sts;
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} sts;
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/* Wait for IRQ, then read PIH irq status (also blocking) */
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wait_for_completion_interruptible(&irq_event);
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/* read INT_STS_A, B and C in one shot using a burst read */
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ret = twl_i2c_read(TWL_MODULE_PIH, sts.bytes,
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REG_INT_STS_A, 3);
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if (ret) {
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pr_warning("twl6030: I2C error %d reading PIH ISR\n",
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ret);
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if (++i2c_errors >= max_i2c_errors) {
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printk(KERN_ERR "Maximum I2C error count"
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" exceeded. Terminating %s.\n",
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__func__);
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break;
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}
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complete(&irq_event);
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continue;
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}
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sts.bytes[3] = 0; /* Only 24 bits are valid*/
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/*
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* Since VBUS status bit is not reliable for VBUS disconnect
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* use CHARGER VBUS detection status bit instead.
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*/
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if (sts.bytes[2] & 0x10)
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sts.bytes[2] |= 0x08;
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for (i = 0; sts.int_sts; sts.int_sts >>= 1, i++) {
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local_irq_disable();
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if (sts.int_sts & 0x1) {
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int module_irq = twl6030_irq_base +
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twl6030_interrupt_mapping[i];
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generic_handle_irq(module_irq);
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}
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local_irq_enable();
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}
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/*
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* NOTE:
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* Simulation confirms that documentation is wrong w.r.t the
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* interrupt status clear operation. A single *byte* write to
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* any one of STS_A to STS_C register results in all three
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* STS registers being reset. Since it does not matter which
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* value is written, all three registers are cleared on a
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* single byte write, so we just use 0x0 to clear.
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*/
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ret = twl_i2c_write_u8(TWL_MODULE_PIH, 0x00, REG_INT_STS_A);
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if (ret)
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pr_warning("twl6030: I2C error in clearing PIH ISR\n");
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enable_irq(irq);
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}
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return 0;
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}
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/*
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* handle_twl6030_int() is the desc->handle method for the twl6030 interrupt.
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* This is a chained interrupt, so there is no desc->action method for it.
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* Now we need to query the interrupt controller in the twl6030 to determine
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* which module is generating the interrupt request. However, we can't do i2c
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* transactions in interrupt context, so we must defer that work to a kernel
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* thread. All we do here is acknowledge and mask the interrupt and wakeup
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* the kernel thread.
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*/
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static irqreturn_t handle_twl6030_pih(int irq, void *devid)
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{
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disable_irq_nosync(irq);
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complete(devid);
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return IRQ_HANDLED;
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}
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/*----------------------------------------------------------------------*/
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static inline void activate_irq(int irq)
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{
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#ifdef CONFIG_ARM
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/* ARM requires an extra step to clear IRQ_NOREQUEST, which it
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* sets on behalf of every irq_chip. Also sets IRQ_NOPROBE.
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*/
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set_irq_flags(irq, IRQF_VALID);
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#else
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/* same effect on other architectures */
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irq_set_noprobe(irq);
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#endif
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}
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static int twl6030_irq_set_wake(struct irq_data *d, unsigned int on)
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{
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if (on)
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atomic_inc(&twl6030_wakeirqs);
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else
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atomic_dec(&twl6030_wakeirqs);
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return 0;
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}
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int twl6030_interrupt_unmask(u8 bit_mask, u8 offset)
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{
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int ret;
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u8 unmask_value;
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ret = twl_i2c_read_u8(TWL_MODULE_PIH, &unmask_value,
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REG_INT_STS_A + offset);
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unmask_value &= (~(bit_mask));
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ret |= twl_i2c_write_u8(TWL_MODULE_PIH, unmask_value,
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REG_INT_STS_A + offset); /* unmask INT_MSK_A/B/C */
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return ret;
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}
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EXPORT_SYMBOL(twl6030_interrupt_unmask);
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int twl6030_interrupt_mask(u8 bit_mask, u8 offset)
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{
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int ret;
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u8 mask_value;
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ret = twl_i2c_read_u8(TWL_MODULE_PIH, &mask_value,
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REG_INT_STS_A + offset);
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mask_value |= (bit_mask);
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ret |= twl_i2c_write_u8(TWL_MODULE_PIH, mask_value,
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REG_INT_STS_A + offset); /* mask INT_MSK_A/B/C */
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return ret;
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}
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EXPORT_SYMBOL(twl6030_interrupt_mask);
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int twl6030_mmc_card_detect_config(void)
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{
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int ret;
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u8 reg_val = 0;
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/* Unmasking the Card detect Interrupt line for MMC1 from Phoenix */
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twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
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REG_INT_MSK_LINE_B);
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twl6030_interrupt_unmask(TWL6030_MMCDETECT_INT_MASK,
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REG_INT_MSK_STS_B);
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/*
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* Initially Configuring MMC_CTRL for receiving interrupts &
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* Card status on TWL6030 for MMC1
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*/
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ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val, TWL6030_MMCCTRL);
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if (ret < 0) {
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pr_err("twl6030: Failed to read MMCCTRL, error %d\n", ret);
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return ret;
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}
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reg_val &= ~VMMC_AUTO_OFF;
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reg_val |= SW_FC;
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ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val, TWL6030_MMCCTRL);
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if (ret < 0) {
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pr_err("twl6030: Failed to write MMCCTRL, error %d\n", ret);
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return ret;
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}
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/* Configuring PullUp-PullDown register */
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ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, ®_val,
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TWL6030_CFG_INPUT_PUPD3);
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if (ret < 0) {
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pr_err("twl6030: Failed to read CFG_INPUT_PUPD3, error %d\n",
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ret);
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return ret;
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}
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reg_val &= ~(MMC_PU | MMC_PD);
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ret = twl_i2c_write_u8(TWL6030_MODULE_ID0, reg_val,
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TWL6030_CFG_INPUT_PUPD3);
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if (ret < 0) {
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pr_err("twl6030: Failed to write CFG_INPUT_PUPD3, error %d\n",
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ret);
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return ret;
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}
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return twl6030_irq_base + MMCDETECT_INTR_OFFSET;
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}
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EXPORT_SYMBOL(twl6030_mmc_card_detect_config);
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int twl6030_mmc_card_detect(struct device *dev, int slot)
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{
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int ret = -EIO;
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u8 read_reg = 0;
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struct platform_device *pdev = to_platform_device(dev);
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if (pdev->id) {
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/* TWL6030 provide's Card detect support for
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* only MMC1 controller.
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*/
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pr_err("Unknown MMC controller %d in %s\n", pdev->id, __func__);
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return ret;
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}
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/*
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* BIT0 of MMC_CTRL on TWL6030 provides card status for MMC1
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* 0 - Card not present ,1 - Card present
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*/
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ret = twl_i2c_read_u8(TWL6030_MODULE_ID0, &read_reg,
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TWL6030_MMCCTRL);
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if (ret >= 0)
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ret = read_reg & STS_MMC;
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return ret;
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}
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EXPORT_SYMBOL(twl6030_mmc_card_detect);
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int twl6030_init_irq(struct device *dev, int irq_num)
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{
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struct device_node *node = dev->of_node;
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int nr_irqs, irq_base, irq_end;
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struct task_struct *task;
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static struct irq_chip twl6030_irq_chip;
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int status = 0;
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int i;
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u8 mask[3];
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nr_irqs = TWL6030_NR_IRQS;
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irq_base = irq_alloc_descs(-1, 0, nr_irqs, 0);
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if (IS_ERR_VALUE(irq_base)) {
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dev_err(dev, "Fail to allocate IRQ descs\n");
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return irq_base;
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}
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irq_domain_add_legacy(node, nr_irqs, irq_base, 0,
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&irq_domain_simple_ops, NULL);
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irq_end = irq_base + nr_irqs;
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mask[0] = 0xFF;
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mask[1] = 0xFF;
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mask[2] = 0xFF;
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/* mask all int lines */
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twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_LINE_A, 3);
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/* mask all int sts */
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twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_MSK_STS_A, 3);
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/* clear INT_STS_A,B,C */
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twl_i2c_write(TWL_MODULE_PIH, &mask[0], REG_INT_STS_A, 3);
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twl6030_irq_base = irq_base;
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/*
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* install an irq handler for each of the modules;
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* clone dummy irq_chip since PIH can't *do* anything
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*/
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twl6030_irq_chip = dummy_irq_chip;
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twl6030_irq_chip.name = "twl6030";
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twl6030_irq_chip.irq_set_type = NULL;
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twl6030_irq_chip.irq_set_wake = twl6030_irq_set_wake;
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for (i = irq_base; i < irq_end; i++) {
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irq_set_chip_and_handler(i, &twl6030_irq_chip,
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handle_simple_irq);
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irq_set_chip_data(i, (void *)irq_num);
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activate_irq(i);
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}
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dev_info(dev, "PIH (irq %d) chaining IRQs %d..%d\n",
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irq_num, irq_base, irq_end);
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/* install an irq handler to demultiplex the TWL6030 interrupt */
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init_completion(&irq_event);
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status = request_irq(irq_num, handle_twl6030_pih, 0, "TWL6030-PIH",
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&irq_event);
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if (status < 0) {
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dev_err(dev, "could not claim irq %d: %d\n", irq_num, status);
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goto fail_irq;
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}
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task = kthread_run(twl6030_irq_thread, (void *)irq_num, "twl6030-irq");
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if (IS_ERR(task)) {
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dev_err(dev, "could not create irq %d thread!\n", irq_num);
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status = PTR_ERR(task);
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goto fail_kthread;
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}
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twl_irq = irq_num;
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register_pm_notifier(&twl6030_irq_pm_notifier_block);
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return irq_base;
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fail_kthread:
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free_irq(irq_num, &irq_event);
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fail_irq:
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for (i = irq_base; i < irq_end; i++)
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irq_set_chip_and_handler(i, NULL, NULL);
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return status;
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}
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int twl6030_exit_irq(void)
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{
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unregister_pm_notifier(&twl6030_irq_pm_notifier_block);
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if (twl6030_irq_base) {
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pr_err("twl6030: can't yet clean up IRQs?\n");
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return -ENOSYS;
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}
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return 0;
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}
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