AuxXxilium/linux_dsm_epyc7002
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b96b3a06d1
linux_dsm_epyc7002/drivers/gpu
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Hai Li b96b3a06d1 drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH 
This change takes advantage of a HW feature that synchronize
flush operation on CTL1 to CTL0, to keep dual DSI pipes in
sync.

Signed-off-by: Hai Li <hali@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>
2015-08-15 18:27:16 -04:00
..
drm drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH 2015-08-15 18:27:16 -04:00
host1x
ipu-v3 GPU: ipu: fix lockup caused by pending chained interrupts 2015-07-10 11:02:46 +02:00
vga vga_switcheroo: Remove unnecessary checks 2015-08-12 17:13:19 +02:00
Makefile