mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
b9581b8488
Use runtime CPU detection to setup all USB parts. Remove the Au1200 OTG and UDC platform devices since there are no drivers for them anyway. Clean up the USB address mess in the au1000 header. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2703/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
536 lines
14 KiB
C
536 lines
14 KiB
C
/*
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* Platform device support for Au1x00 SoCs.
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*
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* Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
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*
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* (C) Copyright Embedded Alley Solutions, Inc 2005
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* Author: Pantelis Antoniou <pantelis@embeddedalley.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/dma-mapping.h>
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#include <linux/etherdevice.h>
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#include <linux/init.h>
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#include <linux/platform_device.h>
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#include <linux/serial_8250.h>
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#include <linux/slab.h>
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#include <asm/mach-au1x00/au1xxx.h>
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#include <asm/mach-au1x00/au1xxx_dbdma.h>
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#include <asm/mach-au1x00/au1100_mmc.h>
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#include <asm/mach-au1x00/au1xxx_eth.h>
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#include <prom.h>
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static void alchemy_8250_pm(struct uart_port *port, unsigned int state,
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unsigned int old_state)
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{
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#ifdef CONFIG_SERIAL_8250
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switch (state) {
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case 0:
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alchemy_uart_enable(CPHYSADDR(port->membase));
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serial8250_do_pm(port, state, old_state);
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break;
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case 3: /* power off */
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serial8250_do_pm(port, state, old_state);
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alchemy_uart_disable(CPHYSADDR(port->membase));
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break;
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default:
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serial8250_do_pm(port, state, old_state);
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break;
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}
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#endif
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}
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#define PORT(_base, _irq) \
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{ \
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.mapbase = _base, \
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.irq = _irq, \
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.regshift = 2, \
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.iotype = UPIO_AU, \
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.flags = UPF_SKIP_TEST | UPF_IOREMAP | \
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UPF_FIXED_TYPE, \
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.type = PORT_16550A, \
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.pm = alchemy_8250_pm, \
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}
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static struct plat_serial8250_port au1x00_uart_data[][4] __initdata = {
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[ALCHEMY_CPU_AU1000] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1000_UART0_INT),
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PORT(AU1000_UART1_PHYS_ADDR, AU1000_UART1_INT),
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PORT(AU1000_UART2_PHYS_ADDR, AU1000_UART2_INT),
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PORT(AU1000_UART3_PHYS_ADDR, AU1000_UART3_INT),
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},
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[ALCHEMY_CPU_AU1500] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1500_UART0_INT),
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PORT(AU1000_UART3_PHYS_ADDR, AU1500_UART3_INT),
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},
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[ALCHEMY_CPU_AU1100] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1100_UART0_INT),
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PORT(AU1000_UART1_PHYS_ADDR, AU1100_UART1_INT),
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PORT(AU1000_UART3_PHYS_ADDR, AU1100_UART3_INT),
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},
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[ALCHEMY_CPU_AU1550] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1550_UART0_INT),
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PORT(AU1000_UART1_PHYS_ADDR, AU1550_UART1_INT),
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PORT(AU1000_UART3_PHYS_ADDR, AU1550_UART3_INT),
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},
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[ALCHEMY_CPU_AU1200] = {
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PORT(AU1000_UART0_PHYS_ADDR, AU1200_UART0_INT),
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PORT(AU1000_UART1_PHYS_ADDR, AU1200_UART1_INT),
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},
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};
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static struct platform_device au1xx0_uart_device = {
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.name = "serial8250",
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.id = PLAT8250_DEV_AU1X00,
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};
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static void __init alchemy_setup_uarts(int ctype)
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{
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unsigned int uartclk = get_au1x00_uart_baud_base() * 16;
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int s = sizeof(struct plat_serial8250_port);
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int c = alchemy_get_uarts(ctype);
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struct plat_serial8250_port *ports;
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ports = kzalloc(s * (c + 1), GFP_KERNEL);
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if (!ports) {
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printk(KERN_INFO "Alchemy: no memory for UART data\n");
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return;
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}
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memcpy(ports, au1x00_uart_data[ctype], s * c);
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au1xx0_uart_device.dev.platform_data = ports;
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/* Fill up uartclk. */
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for (s = 0; s < c; s++)
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ports[s].uartclk = uartclk;
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if (platform_device_register(&au1xx0_uart_device))
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printk(KERN_INFO "Alchemy: failed to register UARTs\n");
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}
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/* The dmamask must be set for OHCI/EHCI to work */
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static u64 alchemy_ohci_dmamask = DMA_BIT_MASK(32);
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static u64 __maybe_unused alchemy_ehci_dmamask = DMA_BIT_MASK(32);
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static unsigned long alchemy_ohci_data[][2] __initdata = {
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[ALCHEMY_CPU_AU1000] = { AU1000_USB_OHCI_PHYS_ADDR, AU1000_USB_HOST_INT },
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[ALCHEMY_CPU_AU1500] = { AU1000_USB_OHCI_PHYS_ADDR, AU1500_USB_HOST_INT },
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[ALCHEMY_CPU_AU1100] = { AU1000_USB_OHCI_PHYS_ADDR, AU1100_USB_HOST_INT },
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[ALCHEMY_CPU_AU1550] = { AU1550_USB_OHCI_PHYS_ADDR, AU1550_USB_HOST_INT },
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[ALCHEMY_CPU_AU1200] = { AU1200_USB_OHCI_PHYS_ADDR, AU1200_USB_INT },
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};
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static unsigned long alchemy_ehci_data[][2] __initdata = {
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[ALCHEMY_CPU_AU1200] = { AU1200_USB_EHCI_PHYS_ADDR, AU1200_USB_INT },
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};
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static int __init _new_usbres(struct resource **r, struct platform_device **d)
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{
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*r = kzalloc(sizeof(struct resource) * 2, GFP_KERNEL);
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if (!*r)
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return -ENOMEM;
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*d = kzalloc(sizeof(struct platform_device), GFP_KERNEL);
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if (!*d) {
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kfree(*r);
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return -ENOMEM;
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}
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(*d)->dev.coherent_dma_mask = DMA_BIT_MASK(32);
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(*d)->num_resources = 2;
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(*d)->resource = *r;
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return 0;
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}
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static void __init alchemy_setup_usb(int ctype)
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{
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struct resource *res;
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struct platform_device *pdev;
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/* setup OHCI0. Every variant has one */
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if (_new_usbres(&res, &pdev))
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return;
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res[0].start = alchemy_ohci_data[ctype][0];
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res[0].end = res[0].start + 0x100 - 1;
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res[0].flags = IORESOURCE_MEM;
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res[1].start = alchemy_ohci_data[ctype][1];
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res[1].end = res[1].start;
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res[1].flags = IORESOURCE_IRQ;
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pdev->name = "au1xxx-ohci";
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pdev->id = 0;
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pdev->dev.dma_mask = &alchemy_ohci_dmamask;
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if (platform_device_register(pdev))
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printk(KERN_INFO "Alchemy USB: cannot add OHCI0\n");
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/* setup EHCI0: Au1200 */
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if (ctype == ALCHEMY_CPU_AU1200) {
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if (_new_usbres(&res, &pdev))
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return;
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res[0].start = alchemy_ehci_data[ctype][0];
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res[0].end = res[0].start + 0x100 - 1;
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res[0].flags = IORESOURCE_MEM;
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res[1].start = alchemy_ehci_data[ctype][1];
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res[1].end = res[1].start;
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res[1].flags = IORESOURCE_IRQ;
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pdev->name = "au1xxx-ehci";
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pdev->id = 0;
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pdev->dev.dma_mask = &alchemy_ehci_dmamask;
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if (platform_device_register(pdev))
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printk(KERN_INFO "Alchemy USB: cannot add EHCI0\n");
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}
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}
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/*** AU1100 LCD controller ***/
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#ifdef CONFIG_FB_AU1100
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static struct resource au1100_lcd_resources[] = {
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[0] = {
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.start = LCD_PHYS_ADDR,
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.end = LCD_PHYS_ADDR + 0x800 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1100_LCD_INT,
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.end = AU1100_LCD_INT,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 au1100_lcd_dmamask = DMA_BIT_MASK(32);
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static struct platform_device au1100_lcd_device = {
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.name = "au1100-lcd",
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.id = 0,
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.dev = {
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.dma_mask = &au1100_lcd_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.num_resources = ARRAY_SIZE(au1100_lcd_resources),
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.resource = au1100_lcd_resources,
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};
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#endif
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#ifdef CONFIG_SOC_AU1200
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static struct resource au1200_lcd_resources[] = {
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[0] = {
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.start = LCD_PHYS_ADDR,
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.end = LCD_PHYS_ADDR + 0x800 - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1200_LCD_INT,
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.end = AU1200_LCD_INT,
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.flags = IORESOURCE_IRQ,
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}
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};
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static u64 au1200_lcd_dmamask = DMA_BIT_MASK(32);
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static struct platform_device au1200_lcd_device = {
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.name = "au1200-lcd",
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.id = 0,
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.dev = {
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.dma_mask = &au1200_lcd_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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},
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.num_resources = ARRAY_SIZE(au1200_lcd_resources),
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.resource = au1200_lcd_resources,
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};
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static u64 au1xxx_mmc_dmamask = DMA_BIT_MASK(32);
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extern struct au1xmmc_platform_data au1xmmc_platdata[2];
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static struct resource au1200_mmc0_resources[] = {
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[0] = {
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.start = AU1100_SD0_PHYS_ADDR,
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.end = AU1100_SD0_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1200_SD_INT,
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.end = AU1200_SD_INT,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = DSCR_CMD0_SDMS_TX0,
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.end = DSCR_CMD0_SDMS_TX0,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = DSCR_CMD0_SDMS_RX0,
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.end = DSCR_CMD0_SDMS_RX0,
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.flags = IORESOURCE_DMA,
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}
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};
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static struct platform_device au1200_mmc0_device = {
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.name = "au1xxx-mmc",
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.id = 0,
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.dev = {
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.dma_mask = &au1xxx_mmc_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &au1xmmc_platdata[0],
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},
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.num_resources = ARRAY_SIZE(au1200_mmc0_resources),
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.resource = au1200_mmc0_resources,
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};
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#ifndef CONFIG_MIPS_DB1200
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static struct resource au1200_mmc1_resources[] = {
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[0] = {
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.start = AU1100_SD1_PHYS_ADDR,
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.end = AU1100_SD1_PHYS_ADDR + 0xfff,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AU1200_SD_INT,
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.end = AU1200_SD_INT,
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.flags = IORESOURCE_IRQ,
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},
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[2] = {
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.start = DSCR_CMD0_SDMS_TX1,
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.end = DSCR_CMD0_SDMS_TX1,
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.flags = IORESOURCE_DMA,
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},
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[3] = {
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.start = DSCR_CMD0_SDMS_RX1,
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.end = DSCR_CMD0_SDMS_RX1,
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.flags = IORESOURCE_DMA,
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}
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};
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static struct platform_device au1200_mmc1_device = {
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.name = "au1xxx-mmc",
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.id = 1,
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.dev = {
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.dma_mask = &au1xxx_mmc_dmamask,
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.coherent_dma_mask = DMA_BIT_MASK(32),
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.platform_data = &au1xmmc_platdata[1],
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},
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.num_resources = ARRAY_SIZE(au1200_mmc1_resources),
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.resource = au1200_mmc1_resources,
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};
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#endif /* #ifndef CONFIG_MIPS_DB1200 */
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#endif /* #ifdef CONFIG_SOC_AU1200 */
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/* All Alchemy demoboards with I2C have this #define in their headers */
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#ifdef SMBUS_PSC_BASE
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static struct resource pbdb_smbus_resources[] = {
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{
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.start = CPHYSADDR(SMBUS_PSC_BASE),
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.end = CPHYSADDR(SMBUS_PSC_BASE + 0xfffff),
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.flags = IORESOURCE_MEM,
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},
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};
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static struct platform_device pbdb_smbus_device = {
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.name = "au1xpsc_smbus",
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.id = 0, /* bus number */
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.num_resources = ARRAY_SIZE(pbdb_smbus_resources),
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.resource = pbdb_smbus_resources,
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};
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#endif
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/* Macro to help defining the Ethernet MAC resources */
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#define MAC_RES_COUNT 4 /* MAC regs, MAC en, MAC INT, MACDMA regs */
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#define MAC_RES(_base, _enable, _irq, _macdma) \
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{ \
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.start = _base, \
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.end = _base + 0xffff, \
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.flags = IORESOURCE_MEM, \
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}, \
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{ \
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.start = _enable, \
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.end = _enable + 0x3, \
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.flags = IORESOURCE_MEM, \
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}, \
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{ \
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.start = _irq, \
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.end = _irq, \
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.flags = IORESOURCE_IRQ \
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}, \
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{ \
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.start = _macdma, \
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.end = _macdma + 0x1ff, \
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.flags = IORESOURCE_MEM, \
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}
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static struct resource au1xxx_eth0_resources[][MAC_RES_COUNT] __initdata = {
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[ALCHEMY_CPU_AU1000] = {
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MAC_RES(AU1000_MAC0_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR,
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AU1000_MAC0_DMA_INT,
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AU1000_MACDMA0_PHYS_ADDR)
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},
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[ALCHEMY_CPU_AU1500] = {
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MAC_RES(AU1500_MAC0_PHYS_ADDR,
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AU1500_MACEN_PHYS_ADDR,
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AU1500_MAC0_DMA_INT,
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AU1000_MACDMA0_PHYS_ADDR)
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},
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[ALCHEMY_CPU_AU1100] = {
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MAC_RES(AU1000_MAC0_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR,
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AU1100_MAC0_DMA_INT,
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AU1000_MACDMA0_PHYS_ADDR)
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},
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[ALCHEMY_CPU_AU1550] = {
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MAC_RES(AU1000_MAC0_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR,
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AU1550_MAC0_DMA_INT,
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AU1000_MACDMA0_PHYS_ADDR)
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},
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};
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static struct au1000_eth_platform_data au1xxx_eth0_platform_data = {
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.phy1_search_mac0 = 1,
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};
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static struct platform_device au1xxx_eth0_device = {
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.name = "au1000-eth",
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.id = 0,
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.num_resources = MAC_RES_COUNT,
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.dev.platform_data = &au1xxx_eth0_platform_data,
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};
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static struct resource au1xxx_eth1_resources[][MAC_RES_COUNT] __initdata = {
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[ALCHEMY_CPU_AU1000] = {
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MAC_RES(AU1000_MAC1_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR + 4,
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AU1000_MAC1_DMA_INT,
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AU1000_MACDMA1_PHYS_ADDR)
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},
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[ALCHEMY_CPU_AU1500] = {
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MAC_RES(AU1500_MAC1_PHYS_ADDR,
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AU1500_MACEN_PHYS_ADDR + 4,
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AU1500_MAC1_DMA_INT,
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AU1000_MACDMA1_PHYS_ADDR)
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},
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[ALCHEMY_CPU_AU1550] = {
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MAC_RES(AU1000_MAC1_PHYS_ADDR,
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AU1000_MACEN_PHYS_ADDR + 4,
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AU1550_MAC1_DMA_INT,
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AU1000_MACDMA1_PHYS_ADDR)
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},
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};
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static struct au1000_eth_platform_data au1xxx_eth1_platform_data = {
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.phy1_search_mac0 = 1,
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};
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static struct platform_device au1xxx_eth1_device = {
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.name = "au1000-eth",
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.id = 1,
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.num_resources = MAC_RES_COUNT,
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.dev.platform_data = &au1xxx_eth1_platform_data,
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};
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void __init au1xxx_override_eth_cfg(unsigned int port,
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struct au1000_eth_platform_data *eth_data)
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{
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if (!eth_data || port > 1)
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return;
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if (port == 0)
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memcpy(&au1xxx_eth0_platform_data, eth_data,
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sizeof(struct au1000_eth_platform_data));
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else
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memcpy(&au1xxx_eth1_platform_data, eth_data,
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sizeof(struct au1000_eth_platform_data));
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}
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static void __init alchemy_setup_macs(int ctype)
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{
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int ret, i;
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unsigned char ethaddr[6];
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struct resource *macres;
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/* Handle 1st MAC */
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if (alchemy_get_macs(ctype) < 1)
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return;
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macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
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if (!macres) {
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printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
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return;
|
|
}
|
|
memcpy(macres, au1xxx_eth0_resources[ctype],
|
|
sizeof(struct resource) * MAC_RES_COUNT);
|
|
au1xxx_eth0_device.resource = macres;
|
|
|
|
i = prom_get_ethernet_addr(ethaddr);
|
|
if (!i && !is_valid_ether_addr(au1xxx_eth0_platform_data.mac))
|
|
memcpy(au1xxx_eth0_platform_data.mac, ethaddr, 6);
|
|
|
|
ret = platform_device_register(&au1xxx_eth0_device);
|
|
if (ret)
|
|
printk(KERN_INFO "Alchemy: failed to register MAC0\n");
|
|
|
|
|
|
/* Handle 2nd MAC */
|
|
if (alchemy_get_macs(ctype) < 2)
|
|
return;
|
|
|
|
macres = kmalloc(sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
|
|
if (!macres) {
|
|
printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
|
|
return;
|
|
}
|
|
memcpy(macres, au1xxx_eth1_resources[ctype],
|
|
sizeof(struct resource) * MAC_RES_COUNT);
|
|
au1xxx_eth1_device.resource = macres;
|
|
|
|
ethaddr[5] += 1; /* next addr for 2nd MAC */
|
|
if (!i && !is_valid_ether_addr(au1xxx_eth1_platform_data.mac))
|
|
memcpy(au1xxx_eth1_platform_data.mac, ethaddr, 6);
|
|
|
|
/* Register second MAC if enabled in pinfunc */
|
|
if (!(au_readl(SYS_PINFUNC) & (u32)SYS_PF_NI2)) {
|
|
ret = platform_device_register(&au1xxx_eth1_device);
|
|
if (ret)
|
|
printk(KERN_INFO "Alchemy: failed to register MAC1\n");
|
|
}
|
|
}
|
|
|
|
static struct platform_device *au1xxx_platform_devices[] __initdata = {
|
|
#ifdef CONFIG_FB_AU1100
|
|
&au1100_lcd_device,
|
|
#endif
|
|
#ifdef CONFIG_SOC_AU1200
|
|
&au1200_lcd_device,
|
|
&au1200_mmc0_device,
|
|
#ifndef CONFIG_MIPS_DB1200
|
|
&au1200_mmc1_device,
|
|
#endif
|
|
#endif
|
|
#ifdef SMBUS_PSC_BASE
|
|
&pbdb_smbus_device,
|
|
#endif
|
|
};
|
|
|
|
static int __init au1xxx_platform_init(void)
|
|
{
|
|
int err, ctype = alchemy_get_cputype();
|
|
|
|
alchemy_setup_uarts(ctype);
|
|
alchemy_setup_macs(ctype);
|
|
alchemy_setup_usb(ctype);
|
|
|
|
err = platform_add_devices(au1xxx_platform_devices,
|
|
ARRAY_SIZE(au1xxx_platform_devices));
|
|
return err;
|
|
}
|
|
|
|
arch_initcall(au1xxx_platform_init);
|