David Daney b93b2abce4 MIPS: Octeon: Rewrite DMA mapping functions. ... All Octeon chips can support more than 4GB of RAM. Also due to how Octeon PCI is setup, even some configurations with less than 4GB of RAM will have portions that are not accessible from 32-bit devices. Enable the swiotlb code to handle the cases where a device cannot directly do DMA. This is a complete rewrite of the Octeon DMA mapping code. Signed-off-by: David Daney <ddaney@caviumnetworks.com> Patchwork: http://patchwork.linux-mips.org/patch/1639/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2010-10-29 19:08:32 +01:00
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cpu-feature-overrides.h	MIPS: Octeon: Adjust top of DMA32 zone.	2010-10-29 19:08:29 +01:00
dma-coherence.h	MIPS: Octeon: Rewrite DMA mapping functions.	2010-10-29 19:08:32 +01:00
irq.h	MIPS: Octeon: Support 256 MSI on PCIe	2010-08-05 13:26:27 +01:00
kernel-entry-init.h	MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.	2009-01-11 09:57:21 +00:00
war.h	MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.	2009-01-11 09:57:21 +00:00