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f6f9be1c30
This patch adds support for the Broadcom Brahma-B15 CPU readahead cache controller. This cache controller sits between the L2 and the memory bus and its purpose is to provide a friendler burst size towards the DDR interface than the native cache line size. The readahead cache is mostly transparent, except for flush_kern_cache_all, which is precisely what we are overriding here. The readahead cache only intercepts reads, and does invalidate on writes (IOW), as such, some data can remain stale in any of its buffers, such that we need to flush it, which is an operation that needs to happen in a particular order: - disable the readahead cache - flush it - call the appropriate cache-v7.S function - re-enable This patch tries to minimize the impact to the cache-v7.S file by only providing a stub in case CONFIG_CACHE_B15_RAC is enabled (default for ARCH_BRCMSTB since it is the current user). Signed-off-by: Alamy Liu <alamyliu@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
165 lines
3.6 KiB
C
165 lines
3.6 KiB
C
/*
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* arch/arm/include/asm/glue-cache.h
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*
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* Copyright (C) 1999-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef ASM_GLUE_CACHE_H
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#define ASM_GLUE_CACHE_H
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#include <asm/glue.h>
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/*
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* Cache Model
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* ===========
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*/
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#undef _CACHE
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#undef MULTI_CACHE
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#if defined(CONFIG_CPU_CACHE_V4)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v4
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM920T) || defined(CONFIG_CPU_ARM922T) || \
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defined(CONFIG_CPU_ARM925T) || defined(CONFIG_CPU_ARM1020) || \
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defined(CONFIG_CPU_ARM1026)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_FA526)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE fa
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM926T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm926
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM940T)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm940
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# endif
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#endif
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#if defined(CONFIG_CPU_ARM946E)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE arm946
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# endif
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#endif
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#if defined(CONFIG_CPU_CACHE_V4WB)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v4wb
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# endif
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#endif
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#if defined(CONFIG_CPU_XSCALE)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE xscale
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# endif
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#endif
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#if defined(CONFIG_CPU_XSC3)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE xsc3
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# endif
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#endif
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#if defined(CONFIG_CPU_MOHAWK)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE mohawk
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# endif
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#endif
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#if defined(CONFIG_CPU_FEROCEON)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v6
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# endif
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#endif
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#if defined(CONFIG_CPU_V7)
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# ifdef _CACHE
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# define MULTI_CACHE 1
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# else
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# define _CACHE v7
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# endif
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#endif
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#if defined(CONFIG_CACHE_B15_RAC)
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# define MULTI_CACHE 1
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#endif
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#if defined(CONFIG_CPU_V7M)
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# define MULTI_CACHE 1
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#endif
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#if !defined(_CACHE) && !defined(MULTI_CACHE)
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#error Unknown cache maintenance model
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#endif
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#ifndef __ASSEMBLER__
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static inline void nop_flush_icache_all(void) { }
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static inline void nop_flush_kern_cache_all(void) { }
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static inline void nop_flush_kern_cache_louis(void) { }
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static inline void nop_flush_user_cache_all(void) { }
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static inline void nop_flush_user_cache_range(unsigned long a,
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unsigned long b, unsigned int c) { }
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static inline void nop_coherent_kern_range(unsigned long a, unsigned long b) { }
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static inline int nop_coherent_user_range(unsigned long a,
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unsigned long b) { return 0; }
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static inline void nop_flush_kern_dcache_area(void *a, size_t s) { }
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static inline void nop_dma_flush_range(const void *a, const void *b) { }
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static inline void nop_dma_map_area(const void *s, size_t l, int f) { }
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static inline void nop_dma_unmap_area(const void *s, size_t l, int f) { }
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#endif
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#ifndef MULTI_CACHE
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#define __cpuc_flush_icache_all __glue(_CACHE,_flush_icache_all)
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#define __cpuc_flush_kern_all __glue(_CACHE,_flush_kern_cache_all)
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#define __cpuc_flush_kern_louis __glue(_CACHE,_flush_kern_cache_louis)
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#define __cpuc_flush_user_all __glue(_CACHE,_flush_user_cache_all)
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#define __cpuc_flush_user_range __glue(_CACHE,_flush_user_cache_range)
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#define __cpuc_coherent_kern_range __glue(_CACHE,_coherent_kern_range)
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#define __cpuc_coherent_user_range __glue(_CACHE,_coherent_user_range)
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#define __cpuc_flush_dcache_area __glue(_CACHE,_flush_kern_dcache_area)
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#define dmac_flush_range __glue(_CACHE,_dma_flush_range)
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#endif
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#endif
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