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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6b08cd6328
Provide interfaces for recognizing accesses to PMU-related MSRs and LVTPC APIC and process these accesses in Xen PMU code. (The interrupt handler performs XENPMU_flush right away in the beginning since no PMU emulation is available. It will be added with a later patch). Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> Reviewed-by: David Vrabel <david.vrabel@citrix.com> Signed-off-by: David Vrabel <david.vrabel@citrix.com>
221 lines
5.1 KiB
C
221 lines
5.1 KiB
C
#include <linux/init.h>
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#include <asm/x86_init.h>
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#include <asm/apic.h>
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#include <asm/xen/hypercall.h>
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#include <xen/xen.h>
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#include <xen/interface/physdev.h>
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#include "xen-ops.h"
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#include "pmu.h"
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#include "smp.h"
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static unsigned int xen_io_apic_read(unsigned apic, unsigned reg)
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{
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struct physdev_apic apic_op;
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int ret;
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apic_op.apic_physbase = mpc_ioapic_addr(apic);
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apic_op.reg = reg;
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ret = HYPERVISOR_physdev_op(PHYSDEVOP_apic_read, &apic_op);
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if (!ret)
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return apic_op.value;
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/* fallback to return an emulated IO_APIC values */
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if (reg == 0x1)
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return 0x00170020;
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else if (reg == 0x0)
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return apic << 24;
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return 0xfd;
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}
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static unsigned long xen_set_apic_id(unsigned int x)
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{
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WARN_ON(1);
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return x;
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}
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static unsigned int xen_get_apic_id(unsigned long x)
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{
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return ((x)>>24) & 0xFFu;
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}
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static u32 xen_apic_read(u32 reg)
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{
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struct xen_platform_op op = {
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.cmd = XENPF_get_cpuinfo,
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.interface_version = XENPF_INTERFACE_VERSION,
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.u.pcpu_info.xen_cpuid = 0,
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};
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int ret = 0;
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/* Shouldn't need this as APIC is turned off for PV, and we only
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* get called on the bootup processor. But just in case. */
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if (!xen_initial_domain() || smp_processor_id())
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return 0;
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if (reg == APIC_LVR)
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return 0x10;
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#ifdef CONFIG_X86_32
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if (reg == APIC_LDR)
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return SET_APIC_LOGICAL_ID(1UL << smp_processor_id());
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#endif
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if (reg != APIC_ID)
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return 0;
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ret = HYPERVISOR_dom0_op(&op);
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if (ret)
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return 0;
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return op.u.pcpu_info.apic_id << 24;
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}
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static void xen_apic_write(u32 reg, u32 val)
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{
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if (reg == APIC_LVTPC) {
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(void)pmu_apic_update(reg);
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return;
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}
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/* Warn to see if there's any stray references */
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WARN(1,"register: %x, value: %x\n", reg, val);
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}
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static u64 xen_apic_icr_read(void)
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{
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return 0;
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}
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static void xen_apic_icr_write(u32 low, u32 id)
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{
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/* Warn to see if there's any stray references */
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WARN_ON(1);
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}
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static u32 xen_safe_apic_wait_icr_idle(void)
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{
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return 0;
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}
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static int xen_apic_probe_pv(void)
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{
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if (xen_pv_domain())
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return 1;
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return 0;
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}
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static int xen_madt_oem_check(char *oem_id, char *oem_table_id)
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{
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return xen_pv_domain();
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}
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static int xen_id_always_valid(int apicid)
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{
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return 1;
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}
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static int xen_id_always_registered(void)
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{
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return 1;
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}
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static int xen_phys_pkg_id(int initial_apic_id, int index_msb)
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{
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return initial_apic_id >> index_msb;
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}
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#ifdef CONFIG_X86_32
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static int xen_x86_32_early_logical_apicid(int cpu)
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{
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/* Match with APIC_LDR read. Otherwise setup_local_APIC complains. */
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return 1 << cpu;
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}
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#endif
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static void xen_noop(void)
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{
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}
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static void xen_silent_inquire(int apicid)
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{
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}
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static struct apic xen_pv_apic = {
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.name = "Xen PV",
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.probe = xen_apic_probe_pv,
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.acpi_madt_oem_check = xen_madt_oem_check,
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.apic_id_valid = xen_id_always_valid,
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.apic_id_registered = xen_id_always_registered,
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/* .irq_delivery_mode - used in native_compose_msi_msg only */
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/* .irq_dest_mode - used in native_compose_msi_msg only */
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.target_cpus = default_target_cpus,
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.disable_esr = 0,
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/* .dest_logical - default_send_IPI_ use it but we use our own. */
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.check_apicid_used = default_check_apicid_used, /* Used on 32-bit */
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.vector_allocation_domain = flat_vector_allocation_domain,
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.init_apic_ldr = xen_noop, /* setup_local_APIC calls it */
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.ioapic_phys_id_map = default_ioapic_phys_id_map, /* Used on 32-bit */
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.setup_apic_routing = NULL,
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.cpu_present_to_apicid = default_cpu_present_to_apicid,
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.apicid_to_cpu_present = physid_set_mask_of_physid, /* Used on 32-bit */
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.check_phys_apicid_present = default_check_phys_apicid_present, /* smp_sanity_check needs it */
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.phys_pkg_id = xen_phys_pkg_id, /* detect_ht */
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.get_apic_id = xen_get_apic_id,
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.set_apic_id = xen_set_apic_id, /* Can be NULL on 32-bit. */
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.apic_id_mask = 0xFF << 24, /* Used by verify_local_APIC. Match with what xen_get_apic_id does. */
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.cpu_mask_to_apicid_and = flat_cpu_mask_to_apicid_and,
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#ifdef CONFIG_SMP
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.send_IPI_mask = xen_send_IPI_mask,
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.send_IPI_mask_allbutself = xen_send_IPI_mask_allbutself,
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.send_IPI_allbutself = xen_send_IPI_allbutself,
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.send_IPI_all = xen_send_IPI_all,
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.send_IPI_self = xen_send_IPI_self,
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#endif
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/* .wait_for_init_deassert- used by AP bootup - smp_callin which we don't use */
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.inquire_remote_apic = xen_silent_inquire,
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.read = xen_apic_read,
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.write = xen_apic_write,
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.eoi_write = xen_apic_write,
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.icr_read = xen_apic_icr_read,
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.icr_write = xen_apic_icr_write,
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.wait_icr_idle = xen_noop,
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.safe_wait_icr_idle = xen_safe_apic_wait_icr_idle,
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#ifdef CONFIG_X86_32
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/* generic_processor_info and setup_local_APIC. */
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.x86_32_early_logical_apicid = xen_x86_32_early_logical_apicid,
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#endif
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};
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static void __init xen_apic_check(void)
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{
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if (apic == &xen_pv_apic)
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return;
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pr_info("Switched APIC routing from %s to %s.\n", apic->name,
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xen_pv_apic.name);
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apic = &xen_pv_apic;
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}
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void __init xen_init_apic(void)
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{
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x86_io_apic_ops.read = xen_io_apic_read;
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/* On PV guests the APIC CPUID bit is disabled so none of the
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* routines end up executing. */
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if (!xen_initial_domain())
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apic = &xen_pv_apic;
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x86_platform.apic_post_init = xen_apic_check;
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}
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apic_driver(xen_pv_apic);
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