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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a503cf0cbe
Broadcom OHCI and EHCI controllers always have 2 ports each on the root hub. Describe them in DT to allow specifying extra info or referencing port nodes. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
182 lines
3.6 KiB
Plaintext
182 lines
3.6 KiB
Plaintext
/*
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* Copyright (C) 2016 Rafał Miłecki <rafal@milecki.pl>
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*
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* Licensed under the ISC license.
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "skeleton.dtsi"
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/ {
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interrupt-parent = <&gic>;
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chosen {
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stdout-path = &uart0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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};
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};
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mpcore {
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compatible = "simple-bus";
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ranges = <0x00000000 0x18310000 0x00008000>;
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#address-cells = <1>;
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#size-cells = <1>;
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gic: interrupt-controller@1000 {
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compatible = "arm,cortex-a7-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1000 0x1000>,
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<0x2000 0x0100>;
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};
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};
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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alp: oscillator {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <40000000>;
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};
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};
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axi@18000000 {
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compatible = "brcm,bus-axi";
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reg = <0x18000000 0x1000>;
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ranges = <0x00000000 0x18000000 0x00100000>;
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#address-cells = <1>;
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#size-cells = <1>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0x000fffff 0xffff>;
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interrupt-map =
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/* ChipCommon */
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<0x00000000 0 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
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/* IEEE 802.11 0 */
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<0x00001000 0 &gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
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/* PCIe Controller 0 */
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<0x00002000 0 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0x00002000 1 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0x00002000 2 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0x00002000 3 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0x00002000 4 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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<0x00002000 5 &gic GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
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/* USB 2.0 Controller */
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<0x00004000 0 &gic GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 0 */
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<0x00005000 0 &gic GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
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/* IEEE 802.11 1 */
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<0x0000a000 0 &gic GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
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/* Ethernet Controller 1 */
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<0x0000b000 0 &gic GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
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chipcommon: chipcommon@0 {
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compatible = "simple-bus";
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reg = <0x00000000 0x1000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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gpio-controller;
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#gpio-cells = <2>;
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uart0: serial@0300 {
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compatible = "ns16550a";
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reg = <0x0300 0x100>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 16 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&alp>;
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status = "okay";
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};
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};
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usb2: usb2@4000 {
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reg = <0x4000 0x1000>;
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ranges;
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#address-cells = <1>;
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#size-cells = <1>;
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ehci: ehci@4000 {
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compatible = "generic-ehci";
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reg = <0x4000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ehci_port1: port@1 {
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reg = <1>;
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};
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ehci_port2: port@2 {
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reg = <2>;
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};
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};
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ohci: ohci@d000 {
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#usb-cells = <0>;
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compatible = "generic-ohci";
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reg = <0xd000 0x1000>;
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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#address-cells = <1>;
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#size-cells = <0>;
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ohci_port1: port@1 {
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reg = <1>;
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};
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ohci_port2: port@2 {
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reg = <2>;
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};
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};
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};
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gmac0: ethernet@5000 {
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reg = <0x5000 0x1000>;
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};
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gmac1: ethernet@b000 {
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reg = <0xb000 0x1000>;
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};
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pmu@12000 {
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compatible = "simple-mfd", "syscon";
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reg = <0x00012000 0x00001000>;
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ilp: ilp {
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compatible = "brcm,bcm53573-ilp";
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clocks = <&alp>;
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#clock-cells = <0>;
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clock-output-names = "ilp";
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};
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};
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};
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};
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