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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 08:06:49 +07:00
e540920cf2
Recent patch by Tomasz Figa ("irqchip: gic: Fix core ID calculation
when topology is read from DT") fixed GIC driver to filter cluster ID
from values returned by cpu_logical_map() for SoCs having registers
mapped without per-CPU banking making it is possible to add CPU nodes
for Exynos4 SoCs. In case of Exynos SoCs these CPU nodes are also
required by future changes adding initialization of cpuidle states in
Exynos cpuidle driver through DT.
Tested on Origen board (Exynos4210 SoC) and Trats2 (Exynos4412 SoC).
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
50 lines
1.1 KiB
Plaintext
50 lines
1.1 KiB
Plaintext
/*
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* Samsung's Exynos4212 SoC device tree source
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* Samsung's Exynos4212 SoC device nodes are listed in this file. Exynos4212
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* based board files can include this file and provide values for board specfic
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* bindings.
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*
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* Note: This file does not include device nodes for all the controllers in
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* Exynos4212 SoC. As device tree coverage for Exynos4212 increases, additional
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* nodes can be added to this file.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include "exynos4x12.dtsi"
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/ {
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compatible = "samsung,exynos4212", "samsung,exynos4";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@A00 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xA00>;
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};
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cpu@A01 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0xA01>;
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};
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};
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combiner: interrupt-controller@10440000 {
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samsung,combiner-nr = <18>;
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};
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gic: interrupt-controller@10490000 {
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cpu-offset = <0x8000>;
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};
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};
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