mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 15:46:52 +07:00
6656920b0b
Add support for processors that have cache-aliasing issues, such as the Stretch S5000 processor. Cache-aliasing means that the size of the cache (for one way) is larger than the page size, thus, a page can end up in several places in cache depending on the virtual to physical translation. The method used here is to map a user page temporarily through the auto-refill way 0 and of of the DTLB. We probably will want to revisit this issue and use a better approach with kmap/kunmap. Signed-off-by: Chris Zankel <chris@zankel.net>
34 lines
932 B
C
34 lines
932 B
C
/*
|
|
* include/asm-xtensa/cache.h
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* (C) 2001 - 2005 Tensilica Inc.
|
|
*/
|
|
|
|
#ifndef _XTENSA_CACHE_H
|
|
#define _XTENSA_CACHE_H
|
|
|
|
#include <asm/variant/core.h>
|
|
|
|
#define L1_CACHE_SHIFT XCHAL_DCACHE_LINEWIDTH
|
|
#define L1_CACHE_BYTES XCHAL_DCACHE_LINESIZE
|
|
#define SMP_CACHE_BYTES L1_CACHE_BYTES
|
|
|
|
#define DCACHE_WAY_SIZE (XCHAL_DCACHE_SIZE/XCHAL_DCACHE_WAYS)
|
|
#define ICACHE_WAY_SIZE (XCHAL_ICACHE_SIZE/XCHAL_ICACHE_WAYS)
|
|
#define DCACHE_WAY_SHIFT (XCHAL_DCACHE_SETWIDTH + XCHAL_DCACHE_LINEWIDTH)
|
|
#define ICACHE_WAY_SHIFT (XCHAL_ICACHE_SETWIDTH + XCHAL_ICACHE_LINEWIDTH)
|
|
|
|
/* Maximum cache size per way. */
|
|
#if DCACHE_WAY_SIZE >= ICACHE_WAY_SIZE
|
|
# define CACHE_WAY_SIZE DCACHE_WAY_SIZE
|
|
#else
|
|
# define CACHE_WAY_SIZE ICACHE_WAY_SIZE
|
|
#endif
|
|
|
|
|
|
#endif /* _XTENSA_CACHE_H */
|