Gregory CLEMENT b8db6b886a ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl ... Aurora Cache Controller was designed to be compatible with the ARM L2 Cache Controller. It comes with some difference or improvement such as: - no cache id part number available through hardware (need to get it by the DT). - always write through mode available. - two flavors of the controller outer cache and system cache (meaning maintenance operations on L1 are broadcasted to the L2 and L2 performs the same operation). - in outer cache mode, the cache maintenance operations are improved and can be done on a range inside a page and are not limited to a cache line. Tested-and-Reviewed-by: Lior Amsalem <alior@marvell.com> Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Yehuda Yitschak <yehuday@marvell.com> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>		2012-11-06 19:47:35 +00:00
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asm	ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl	2012-11-06 19:47:35 +00:00
debug	ARM: picoxcell: move debug macros to include/debug	2012-09-14 09:22:03 -05:00
uapi/asm	UAPI: (Scripted) Disintegrate arch/arm/include/asm	2012-10-12 13:05:52 +01:00