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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 06:43:52 +07:00
862a336c83
The patch adds support for "outside the context of a BSS"(OCB) mode to ath9k driver and extends debugfs files by OCB ralated information. This patch was tested on AR9380-AL1A cards. Signed-off-by: Jan Kaisrlik <kaisrja1@fel.cvut.cz> Cc: Michal Sojka <sojkam1@fel.cvut.cz> Signed-off-by: Kalle Valo <kvalo@codeaurora.org>
1171 lines
29 KiB
C
1171 lines
29 KiB
C
/*
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* Copyright (c) 2008-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <linux/dma-mapping.h>
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#include "ath9k.h"
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#include "ar9003_mac.h"
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#define SKB_CB_ATHBUF(__skb) (*((struct ath_rxbuf **)__skb->cb))
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static inline bool ath9k_check_auto_sleep(struct ath_softc *sc)
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{
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return sc->ps_enabled &&
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(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP);
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}
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/*
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* Setup and link descriptors.
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*
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* 11N: we can no longer afford to self link the last descriptor.
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* MAC acknowledges BA status as long as it copies frames to host
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* buffer (or rx fifo). This can incorrectly acknowledge packets
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* to a sender if last desc is self-linked.
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*/
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static void ath_rx_buf_link(struct ath_softc *sc, struct ath_rxbuf *bf,
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bool flush)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_desc *ds;
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struct sk_buff *skb;
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ds = bf->bf_desc;
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ds->ds_link = 0; /* link to null */
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ds->ds_data = bf->bf_buf_addr;
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/* virtual addr of the beginning of the buffer. */
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skb = bf->bf_mpdu;
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BUG_ON(skb == NULL);
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ds->ds_vdata = skb->data;
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/*
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* setup rx descriptors. The rx_bufsize here tells the hardware
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* how much data it can DMA to us and that we are prepared
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* to process
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*/
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ath9k_hw_setuprxdesc(ah, ds,
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common->rx_bufsize,
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0);
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if (sc->rx.rxlink)
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*sc->rx.rxlink = bf->bf_daddr;
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else if (!flush)
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ath9k_hw_putrxbuf(ah, bf->bf_daddr);
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sc->rx.rxlink = &ds->ds_link;
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}
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static void ath_rx_buf_relink(struct ath_softc *sc, struct ath_rxbuf *bf,
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bool flush)
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{
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if (sc->rx.buf_hold)
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ath_rx_buf_link(sc, sc->rx.buf_hold, flush);
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sc->rx.buf_hold = bf;
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}
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static void ath_setdefantenna(struct ath_softc *sc, u32 antenna)
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{
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/* XXX block beacon interrupts */
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ath9k_hw_setantenna(sc->sc_ah, antenna);
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sc->rx.defant = antenna;
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sc->rx.rxotherant = 0;
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}
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static void ath_opmode_init(struct ath_softc *sc)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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u32 rfilt, mfilt[2];
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/* configure rx filter */
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rfilt = ath_calcrxfilter(sc);
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ath9k_hw_setrxfilter(ah, rfilt);
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/* configure bssid mask */
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ath_hw_setbssidmask(common);
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/* configure operational mode */
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ath9k_hw_setopmode(ah);
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/* calculate and install multicast filter */
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mfilt[0] = mfilt[1] = ~0;
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ath9k_hw_setmcastfilter(ah, mfilt[0], mfilt[1]);
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}
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static bool ath_rx_edma_buf_link(struct ath_softc *sc,
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enum ath9k_rx_qtype qtype)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_rx_edma *rx_edma;
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struct sk_buff *skb;
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struct ath_rxbuf *bf;
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rx_edma = &sc->rx.rx_edma[qtype];
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if (skb_queue_len(&rx_edma->rx_fifo) >= rx_edma->rx_fifo_hwsize)
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return false;
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bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
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list_del_init(&bf->list);
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skb = bf->bf_mpdu;
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memset(skb->data, 0, ah->caps.rx_status_len);
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dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
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ah->caps.rx_status_len, DMA_TO_DEVICE);
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SKB_CB_ATHBUF(skb) = bf;
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ath9k_hw_addrxbuf_edma(ah, bf->bf_buf_addr, qtype);
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__skb_queue_tail(&rx_edma->rx_fifo, skb);
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return true;
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}
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static void ath_rx_addbuffer_edma(struct ath_softc *sc,
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enum ath9k_rx_qtype qtype)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct ath_rxbuf *bf, *tbf;
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if (list_empty(&sc->rx.rxbuf)) {
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ath_dbg(common, QUEUE, "No free rx buf available\n");
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return;
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}
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list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list)
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if (!ath_rx_edma_buf_link(sc, qtype))
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break;
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}
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static void ath_rx_remove_buffer(struct ath_softc *sc,
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enum ath9k_rx_qtype qtype)
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{
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struct ath_rxbuf *bf;
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struct ath_rx_edma *rx_edma;
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struct sk_buff *skb;
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rx_edma = &sc->rx.rx_edma[qtype];
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while ((skb = __skb_dequeue(&rx_edma->rx_fifo)) != NULL) {
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bf = SKB_CB_ATHBUF(skb);
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BUG_ON(!bf);
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list_add_tail(&bf->list, &sc->rx.rxbuf);
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}
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}
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static void ath_rx_edma_cleanup(struct ath_softc *sc)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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struct ath_rxbuf *bf;
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ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
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ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
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list_for_each_entry(bf, &sc->rx.rxbuf, list) {
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if (bf->bf_mpdu) {
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dma_unmap_single(sc->dev, bf->bf_buf_addr,
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common->rx_bufsize,
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DMA_BIDIRECTIONAL);
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dev_kfree_skb_any(bf->bf_mpdu);
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bf->bf_buf_addr = 0;
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bf->bf_mpdu = NULL;
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}
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}
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}
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static void ath_rx_edma_init_queue(struct ath_rx_edma *rx_edma, int size)
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{
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__skb_queue_head_init(&rx_edma->rx_fifo);
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rx_edma->rx_fifo_hwsize = size;
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}
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static int ath_rx_edma_init(struct ath_softc *sc, int nbufs)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct ath_hw *ah = sc->sc_ah;
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struct sk_buff *skb;
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struct ath_rxbuf *bf;
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int error = 0, i;
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u32 size;
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ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
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ah->caps.rx_status_len);
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ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_LP],
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ah->caps.rx_lp_qdepth);
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ath_rx_edma_init_queue(&sc->rx.rx_edma[ATH9K_RX_QUEUE_HP],
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ah->caps.rx_hp_qdepth);
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size = sizeof(struct ath_rxbuf) * nbufs;
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bf = devm_kzalloc(sc->dev, size, GFP_KERNEL);
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if (!bf)
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return -ENOMEM;
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INIT_LIST_HEAD(&sc->rx.rxbuf);
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for (i = 0; i < nbufs; i++, bf++) {
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skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_KERNEL);
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if (!skb) {
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error = -ENOMEM;
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goto rx_init_fail;
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}
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memset(skb->data, 0, common->rx_bufsize);
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bf->bf_mpdu = skb;
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bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
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common->rx_bufsize,
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DMA_BIDIRECTIONAL);
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if (unlikely(dma_mapping_error(sc->dev,
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bf->bf_buf_addr))) {
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dev_kfree_skb_any(skb);
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bf->bf_mpdu = NULL;
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bf->bf_buf_addr = 0;
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ath_err(common,
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"dma_mapping_error() on RX init\n");
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error = -ENOMEM;
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goto rx_init_fail;
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}
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list_add_tail(&bf->list, &sc->rx.rxbuf);
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}
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return 0;
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rx_init_fail:
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ath_rx_edma_cleanup(sc);
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return error;
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}
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static void ath_edma_start_recv(struct ath_softc *sc)
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{
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ath9k_hw_rxena(sc->sc_ah);
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ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_HP);
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ath_rx_addbuffer_edma(sc, ATH9K_RX_QUEUE_LP);
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ath_opmode_init(sc);
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ath9k_hw_startpcureceive(sc->sc_ah, sc->cur_chan->offchannel);
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}
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static void ath_edma_stop_recv(struct ath_softc *sc)
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{
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ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_HP);
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ath_rx_remove_buffer(sc, ATH9K_RX_QUEUE_LP);
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}
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int ath_rx_init(struct ath_softc *sc, int nbufs)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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struct sk_buff *skb;
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struct ath_rxbuf *bf;
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int error = 0;
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spin_lock_init(&sc->sc_pcu_lock);
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common->rx_bufsize = IEEE80211_MAX_MPDU_LEN / 2 +
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sc->sc_ah->caps.rx_status_len;
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if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
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return ath_rx_edma_init(sc, nbufs);
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ath_dbg(common, CONFIG, "cachelsz %u rxbufsize %u\n",
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common->cachelsz, common->rx_bufsize);
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/* Initialize rx descriptors */
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error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
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"rx", nbufs, 1, 0);
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if (error != 0) {
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ath_err(common,
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"failed to allocate rx descriptors: %d\n",
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error);
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goto err;
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}
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list_for_each_entry(bf, &sc->rx.rxbuf, list) {
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skb = ath_rxbuf_alloc(common, common->rx_bufsize,
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GFP_KERNEL);
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if (skb == NULL) {
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error = -ENOMEM;
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goto err;
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}
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bf->bf_mpdu = skb;
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bf->bf_buf_addr = dma_map_single(sc->dev, skb->data,
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common->rx_bufsize,
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DMA_FROM_DEVICE);
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if (unlikely(dma_mapping_error(sc->dev,
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bf->bf_buf_addr))) {
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dev_kfree_skb_any(skb);
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bf->bf_mpdu = NULL;
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bf->bf_buf_addr = 0;
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ath_err(common,
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"dma_mapping_error() on RX init\n");
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error = -ENOMEM;
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goto err;
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}
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}
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sc->rx.rxlink = NULL;
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err:
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if (error)
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ath_rx_cleanup(sc);
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return error;
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}
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void ath_rx_cleanup(struct ath_softc *sc)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_common *common = ath9k_hw_common(ah);
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struct sk_buff *skb;
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struct ath_rxbuf *bf;
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if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
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ath_rx_edma_cleanup(sc);
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return;
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}
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list_for_each_entry(bf, &sc->rx.rxbuf, list) {
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skb = bf->bf_mpdu;
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if (skb) {
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dma_unmap_single(sc->dev, bf->bf_buf_addr,
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common->rx_bufsize,
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DMA_FROM_DEVICE);
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dev_kfree_skb(skb);
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bf->bf_buf_addr = 0;
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bf->bf_mpdu = NULL;
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}
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}
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}
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/*
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* Calculate the receive filter according to the
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* operating mode and state:
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*
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* o always accept unicast, broadcast, and multicast traffic
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* o maintain current state of phy error reception (the hal
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* may enable phy error frames for noise immunity work)
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* o probe request frames are accepted only when operating in
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* hostap, adhoc, or monitor modes
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* o enable promiscuous mode according to the interface state
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* o accept beacons:
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* - when operating in adhoc mode so the 802.11 layer creates
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* node table entries for peers,
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* - when operating in station mode for collecting rssi data when
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* the station is otherwise quiet, or
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* - when operating as a repeater so we see repeater-sta beacons
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* - when scanning
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*/
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u32 ath_calcrxfilter(struct ath_softc *sc)
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{
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struct ath_common *common = ath9k_hw_common(sc->sc_ah);
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u32 rfilt;
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if (config_enabled(CONFIG_ATH9K_TX99))
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return 0;
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rfilt = ATH9K_RX_FILTER_UCAST | ATH9K_RX_FILTER_BCAST
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| ATH9K_RX_FILTER_MCAST;
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/* if operating on a DFS channel, enable radar pulse detection */
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if (sc->hw->conf.radar_enabled)
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rfilt |= ATH9K_RX_FILTER_PHYRADAR | ATH9K_RX_FILTER_PHYERR;
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spin_lock_bh(&sc->chan_lock);
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if (sc->cur_chan->rxfilter & FIF_PROBE_REQ)
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rfilt |= ATH9K_RX_FILTER_PROBEREQ;
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if (sc->sc_ah->is_monitoring)
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rfilt |= ATH9K_RX_FILTER_PROM;
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if ((sc->cur_chan->rxfilter & FIF_CONTROL) ||
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sc->sc_ah->dynack.enabled)
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rfilt |= ATH9K_RX_FILTER_CONTROL;
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if ((sc->sc_ah->opmode == NL80211_IFTYPE_STATION) &&
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(sc->cur_chan->nvifs <= 1) &&
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!(sc->cur_chan->rxfilter & FIF_BCN_PRBRESP_PROMISC))
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rfilt |= ATH9K_RX_FILTER_MYBEACON;
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else if (sc->sc_ah->opmode != NL80211_IFTYPE_OCB)
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rfilt |= ATH9K_RX_FILTER_BEACON;
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if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
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(sc->cur_chan->rxfilter & FIF_PSPOLL))
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rfilt |= ATH9K_RX_FILTER_PSPOLL;
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if (sc->cur_chandef.width != NL80211_CHAN_WIDTH_20_NOHT)
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rfilt |= ATH9K_RX_FILTER_COMP_BAR;
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if (sc->cur_chan->nvifs > 1 || (sc->cur_chan->rxfilter & FIF_OTHER_BSS)) {
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/* This is needed for older chips */
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if (sc->sc_ah->hw_version.macVersion <= AR_SREV_VERSION_9160)
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rfilt |= ATH9K_RX_FILTER_PROM;
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rfilt |= ATH9K_RX_FILTER_MCAST_BCAST_ALL;
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}
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|
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if (AR_SREV_9550(sc->sc_ah) || AR_SREV_9531(sc->sc_ah) ||
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AR_SREV_9561(sc->sc_ah))
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rfilt |= ATH9K_RX_FILTER_4ADDRESS;
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if (ath9k_is_chanctx_enabled() &&
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test_bit(ATH_OP_SCANNING, &common->op_flags))
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rfilt |= ATH9K_RX_FILTER_BEACON;
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spin_unlock_bh(&sc->chan_lock);
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return rfilt;
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|
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}
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|
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void ath_startrecv(struct ath_softc *sc)
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{
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struct ath_hw *ah = sc->sc_ah;
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struct ath_rxbuf *bf, *tbf;
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|
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if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
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ath_edma_start_recv(sc);
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return;
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}
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|
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if (list_empty(&sc->rx.rxbuf))
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goto start_recv;
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|
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sc->rx.buf_hold = NULL;
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sc->rx.rxlink = NULL;
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list_for_each_entry_safe(bf, tbf, &sc->rx.rxbuf, list) {
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ath_rx_buf_link(sc, bf, false);
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}
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/* We could have deleted elements so the list may be empty now */
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if (list_empty(&sc->rx.rxbuf))
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goto start_recv;
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bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
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ath9k_hw_putrxbuf(ah, bf->bf_daddr);
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ath9k_hw_rxena(ah);
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|
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start_recv:
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ath_opmode_init(sc);
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ath9k_hw_startpcureceive(ah, sc->cur_chan->offchannel);
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}
|
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|
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static void ath_flushrecv(struct ath_softc *sc)
|
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{
|
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if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
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ath_rx_tasklet(sc, 1, true);
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ath_rx_tasklet(sc, 1, false);
|
|
}
|
|
|
|
bool ath_stoprecv(struct ath_softc *sc)
|
|
{
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
bool stopped, reset = false;
|
|
|
|
ath9k_hw_abortpcurecv(ah);
|
|
ath9k_hw_setrxfilter(ah, 0);
|
|
stopped = ath9k_hw_stopdmarecv(ah, &reset);
|
|
|
|
ath_flushrecv(sc);
|
|
|
|
if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
|
|
ath_edma_stop_recv(sc);
|
|
else
|
|
sc->rx.rxlink = NULL;
|
|
|
|
if (!(ah->ah_flags & AH_UNPLUGGED) &&
|
|
unlikely(!stopped)) {
|
|
ath_dbg(ath9k_hw_common(sc->sc_ah), RESET,
|
|
"Failed to stop Rx DMA\n");
|
|
RESET_STAT_INC(sc, RESET_RX_DMA_ERROR);
|
|
}
|
|
return stopped && !reset;
|
|
}
|
|
|
|
static bool ath_beacon_dtim_pending_cab(struct sk_buff *skb)
|
|
{
|
|
/* Check whether the Beacon frame has DTIM indicating buffered bc/mc */
|
|
struct ieee80211_mgmt *mgmt;
|
|
u8 *pos, *end, id, elen;
|
|
struct ieee80211_tim_ie *tim;
|
|
|
|
mgmt = (struct ieee80211_mgmt *)skb->data;
|
|
pos = mgmt->u.beacon.variable;
|
|
end = skb->data + skb->len;
|
|
|
|
while (pos + 2 < end) {
|
|
id = *pos++;
|
|
elen = *pos++;
|
|
if (pos + elen > end)
|
|
break;
|
|
|
|
if (id == WLAN_EID_TIM) {
|
|
if (elen < sizeof(*tim))
|
|
break;
|
|
tim = (struct ieee80211_tim_ie *) pos;
|
|
if (tim->dtim_count != 0)
|
|
break;
|
|
return tim->bitmap_ctrl & 0x01;
|
|
}
|
|
|
|
pos += elen;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
|
|
{
|
|
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
|
bool skip_beacon = false;
|
|
|
|
if (skb->len < 24 + 8 + 2 + 2)
|
|
return;
|
|
|
|
sc->ps_flags &= ~PS_WAIT_FOR_BEACON;
|
|
|
|
if (sc->ps_flags & PS_BEACON_SYNC) {
|
|
sc->ps_flags &= ~PS_BEACON_SYNC;
|
|
ath_dbg(common, PS,
|
|
"Reconfigure beacon timers based on synchronized timestamp\n");
|
|
|
|
#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
|
|
if (ath9k_is_chanctx_enabled()) {
|
|
if (sc->cur_chan == &sc->offchannel.chan)
|
|
skip_beacon = true;
|
|
}
|
|
#endif
|
|
|
|
if (!skip_beacon &&
|
|
!(WARN_ON_ONCE(sc->cur_chan->beacon.beacon_interval == 0)))
|
|
ath9k_set_beacon(sc);
|
|
|
|
ath9k_p2p_beacon_sync(sc);
|
|
}
|
|
|
|
if (ath_beacon_dtim_pending_cab(skb)) {
|
|
/*
|
|
* Remain awake waiting for buffered broadcast/multicast
|
|
* frames. If the last broadcast/multicast frame is not
|
|
* received properly, the next beacon frame will work as
|
|
* a backup trigger for returning into NETWORK SLEEP state,
|
|
* so we are waiting for it as well.
|
|
*/
|
|
ath_dbg(common, PS,
|
|
"Received DTIM beacon indicating buffered broadcast/multicast frame(s)\n");
|
|
sc->ps_flags |= PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON;
|
|
return;
|
|
}
|
|
|
|
if (sc->ps_flags & PS_WAIT_FOR_CAB) {
|
|
/*
|
|
* This can happen if a broadcast frame is dropped or the AP
|
|
* fails to send a frame indicating that all CAB frames have
|
|
* been delivered.
|
|
*/
|
|
sc->ps_flags &= ~PS_WAIT_FOR_CAB;
|
|
ath_dbg(common, PS, "PS wait for CAB frames timed out\n");
|
|
}
|
|
}
|
|
|
|
static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb, bool mybeacon)
|
|
{
|
|
struct ieee80211_hdr *hdr;
|
|
struct ath_common *common = ath9k_hw_common(sc->sc_ah);
|
|
|
|
hdr = (struct ieee80211_hdr *)skb->data;
|
|
|
|
/* Process Beacon and CAB receive in PS state */
|
|
if (((sc->ps_flags & PS_WAIT_FOR_BEACON) || ath9k_check_auto_sleep(sc))
|
|
&& mybeacon) {
|
|
ath_rx_ps_beacon(sc, skb);
|
|
} else if ((sc->ps_flags & PS_WAIT_FOR_CAB) &&
|
|
(ieee80211_is_data(hdr->frame_control) ||
|
|
ieee80211_is_action(hdr->frame_control)) &&
|
|
is_multicast_ether_addr(hdr->addr1) &&
|
|
!ieee80211_has_moredata(hdr->frame_control)) {
|
|
/*
|
|
* No more broadcast/multicast frames to be received at this
|
|
* point.
|
|
*/
|
|
sc->ps_flags &= ~(PS_WAIT_FOR_CAB | PS_WAIT_FOR_BEACON);
|
|
ath_dbg(common, PS,
|
|
"All PS CAB frames received, back to sleep\n");
|
|
} else if ((sc->ps_flags & PS_WAIT_FOR_PSPOLL_DATA) &&
|
|
!is_multicast_ether_addr(hdr->addr1) &&
|
|
!ieee80211_has_morefrags(hdr->frame_control)) {
|
|
sc->ps_flags &= ~PS_WAIT_FOR_PSPOLL_DATA;
|
|
ath_dbg(common, PS,
|
|
"Going back to sleep after having received PS-Poll data (0x%lx)\n",
|
|
sc->ps_flags & (PS_WAIT_FOR_BEACON |
|
|
PS_WAIT_FOR_CAB |
|
|
PS_WAIT_FOR_PSPOLL_DATA |
|
|
PS_WAIT_FOR_TX_ACK));
|
|
}
|
|
}
|
|
|
|
static bool ath_edma_get_buffers(struct ath_softc *sc,
|
|
enum ath9k_rx_qtype qtype,
|
|
struct ath_rx_status *rs,
|
|
struct ath_rxbuf **dest)
|
|
{
|
|
struct ath_rx_edma *rx_edma = &sc->rx.rx_edma[qtype];
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
struct sk_buff *skb;
|
|
struct ath_rxbuf *bf;
|
|
int ret;
|
|
|
|
skb = skb_peek(&rx_edma->rx_fifo);
|
|
if (!skb)
|
|
return false;
|
|
|
|
bf = SKB_CB_ATHBUF(skb);
|
|
BUG_ON(!bf);
|
|
|
|
dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
|
|
common->rx_bufsize, DMA_FROM_DEVICE);
|
|
|
|
ret = ath9k_hw_process_rxdesc_edma(ah, rs, skb->data);
|
|
if (ret == -EINPROGRESS) {
|
|
/*let device gain the buffer again*/
|
|
dma_sync_single_for_device(sc->dev, bf->bf_buf_addr,
|
|
common->rx_bufsize, DMA_FROM_DEVICE);
|
|
return false;
|
|
}
|
|
|
|
__skb_unlink(skb, &rx_edma->rx_fifo);
|
|
if (ret == -EINVAL) {
|
|
/* corrupt descriptor, skip this one and the following one */
|
|
list_add_tail(&bf->list, &sc->rx.rxbuf);
|
|
ath_rx_edma_buf_link(sc, qtype);
|
|
|
|
skb = skb_peek(&rx_edma->rx_fifo);
|
|
if (skb) {
|
|
bf = SKB_CB_ATHBUF(skb);
|
|
BUG_ON(!bf);
|
|
|
|
__skb_unlink(skb, &rx_edma->rx_fifo);
|
|
list_add_tail(&bf->list, &sc->rx.rxbuf);
|
|
ath_rx_edma_buf_link(sc, qtype);
|
|
}
|
|
|
|
bf = NULL;
|
|
}
|
|
|
|
*dest = bf;
|
|
return true;
|
|
}
|
|
|
|
static struct ath_rxbuf *ath_edma_get_next_rx_buf(struct ath_softc *sc,
|
|
struct ath_rx_status *rs,
|
|
enum ath9k_rx_qtype qtype)
|
|
{
|
|
struct ath_rxbuf *bf = NULL;
|
|
|
|
while (ath_edma_get_buffers(sc, qtype, rs, &bf)) {
|
|
if (!bf)
|
|
continue;
|
|
|
|
return bf;
|
|
}
|
|
return NULL;
|
|
}
|
|
|
|
static struct ath_rxbuf *ath_get_next_rx_buf(struct ath_softc *sc,
|
|
struct ath_rx_status *rs)
|
|
{
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
struct ath_desc *ds;
|
|
struct ath_rxbuf *bf;
|
|
int ret;
|
|
|
|
if (list_empty(&sc->rx.rxbuf)) {
|
|
sc->rx.rxlink = NULL;
|
|
return NULL;
|
|
}
|
|
|
|
bf = list_first_entry(&sc->rx.rxbuf, struct ath_rxbuf, list);
|
|
if (bf == sc->rx.buf_hold)
|
|
return NULL;
|
|
|
|
ds = bf->bf_desc;
|
|
|
|
/*
|
|
* Must provide the virtual address of the current
|
|
* descriptor, the physical address, and the virtual
|
|
* address of the next descriptor in the h/w chain.
|
|
* This allows the HAL to look ahead to see if the
|
|
* hardware is done with a descriptor by checking the
|
|
* done bit in the following descriptor and the address
|
|
* of the current descriptor the DMA engine is working
|
|
* on. All this is necessary because of our use of
|
|
* a self-linked list to avoid rx overruns.
|
|
*/
|
|
ret = ath9k_hw_rxprocdesc(ah, ds, rs);
|
|
if (ret == -EINPROGRESS) {
|
|
struct ath_rx_status trs;
|
|
struct ath_rxbuf *tbf;
|
|
struct ath_desc *tds;
|
|
|
|
memset(&trs, 0, sizeof(trs));
|
|
if (list_is_last(&bf->list, &sc->rx.rxbuf)) {
|
|
sc->rx.rxlink = NULL;
|
|
return NULL;
|
|
}
|
|
|
|
tbf = list_entry(bf->list.next, struct ath_rxbuf, list);
|
|
|
|
/*
|
|
* On some hardware the descriptor status words could
|
|
* get corrupted, including the done bit. Because of
|
|
* this, check if the next descriptor's done bit is
|
|
* set or not.
|
|
*
|
|
* If the next descriptor's done bit is set, the current
|
|
* descriptor has been corrupted. Force s/w to discard
|
|
* this descriptor and continue...
|
|
*/
|
|
|
|
tds = tbf->bf_desc;
|
|
ret = ath9k_hw_rxprocdesc(ah, tds, &trs);
|
|
if (ret == -EINPROGRESS)
|
|
return NULL;
|
|
|
|
/*
|
|
* Re-check previous descriptor, in case it has been filled
|
|
* in the mean time.
|
|
*/
|
|
ret = ath9k_hw_rxprocdesc(ah, ds, rs);
|
|
if (ret == -EINPROGRESS) {
|
|
/*
|
|
* mark descriptor as zero-length and set the 'more'
|
|
* flag to ensure that both buffers get discarded
|
|
*/
|
|
rs->rs_datalen = 0;
|
|
rs->rs_more = true;
|
|
}
|
|
}
|
|
|
|
list_del(&bf->list);
|
|
if (!bf->bf_mpdu)
|
|
return bf;
|
|
|
|
/*
|
|
* Synchronize the DMA transfer with CPU before
|
|
* 1. accessing the frame
|
|
* 2. requeueing the same buffer to h/w
|
|
*/
|
|
dma_sync_single_for_cpu(sc->dev, bf->bf_buf_addr,
|
|
common->rx_bufsize,
|
|
DMA_FROM_DEVICE);
|
|
|
|
return bf;
|
|
}
|
|
|
|
static void ath9k_process_tsf(struct ath_rx_status *rs,
|
|
struct ieee80211_rx_status *rxs,
|
|
u64 tsf)
|
|
{
|
|
u32 tsf_lower = tsf & 0xffffffff;
|
|
|
|
rxs->mactime = (tsf & ~0xffffffffULL) | rs->rs_tstamp;
|
|
if (rs->rs_tstamp > tsf_lower &&
|
|
unlikely(rs->rs_tstamp - tsf_lower > 0x10000000))
|
|
rxs->mactime -= 0x100000000ULL;
|
|
|
|
if (rs->rs_tstamp < tsf_lower &&
|
|
unlikely(tsf_lower - rs->rs_tstamp > 0x10000000))
|
|
rxs->mactime += 0x100000000ULL;
|
|
}
|
|
|
|
/*
|
|
* For Decrypt or Demic errors, we only mark packet status here and always push
|
|
* up the frame up to let mac80211 handle the actual error case, be it no
|
|
* decryption key or real decryption error. This let us keep statistics there.
|
|
*/
|
|
static int ath9k_rx_skb_preprocess(struct ath_softc *sc,
|
|
struct sk_buff *skb,
|
|
struct ath_rx_status *rx_stats,
|
|
struct ieee80211_rx_status *rx_status,
|
|
bool *decrypt_error, u64 tsf)
|
|
{
|
|
struct ieee80211_hw *hw = sc->hw;
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
struct ieee80211_hdr *hdr;
|
|
bool discard_current = sc->rx.discard_next;
|
|
|
|
/*
|
|
* Discard corrupt descriptors which are marked in
|
|
* ath_get_next_rx_buf().
|
|
*/
|
|
if (discard_current)
|
|
goto corrupt;
|
|
|
|
sc->rx.discard_next = false;
|
|
|
|
/*
|
|
* Discard zero-length packets.
|
|
*/
|
|
if (!rx_stats->rs_datalen) {
|
|
RX_STAT_INC(rx_len_err);
|
|
goto corrupt;
|
|
}
|
|
|
|
/*
|
|
* rs_status follows rs_datalen so if rs_datalen is too large
|
|
* we can take a hint that hardware corrupted it, so ignore
|
|
* those frames.
|
|
*/
|
|
if (rx_stats->rs_datalen > (common->rx_bufsize - ah->caps.rx_status_len)) {
|
|
RX_STAT_INC(rx_len_err);
|
|
goto corrupt;
|
|
}
|
|
|
|
/* Only use status info from the last fragment */
|
|
if (rx_stats->rs_more)
|
|
return 0;
|
|
|
|
/*
|
|
* Return immediately if the RX descriptor has been marked
|
|
* as corrupt based on the various error bits.
|
|
*
|
|
* This is different from the other corrupt descriptor
|
|
* condition handled above.
|
|
*/
|
|
if (rx_stats->rs_status & ATH9K_RXERR_CORRUPT_DESC)
|
|
goto corrupt;
|
|
|
|
hdr = (struct ieee80211_hdr *) (skb->data + ah->caps.rx_status_len);
|
|
|
|
ath9k_process_tsf(rx_stats, rx_status, tsf);
|
|
ath_debug_stat_rx(sc, rx_stats);
|
|
|
|
/*
|
|
* Process PHY errors and return so that the packet
|
|
* can be dropped.
|
|
*/
|
|
if (rx_stats->rs_status & ATH9K_RXERR_PHY) {
|
|
ath9k_dfs_process_phyerr(sc, hdr, rx_stats, rx_status->mactime);
|
|
if (ath_cmn_process_fft(&sc->spec_priv, hdr, rx_stats, rx_status->mactime))
|
|
RX_STAT_INC(rx_spectral);
|
|
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* everything but the rate is checked here, the rate check is done
|
|
* separately to avoid doing two lookups for a rate for each frame.
|
|
*/
|
|
spin_lock_bh(&sc->chan_lock);
|
|
if (!ath9k_cmn_rx_accept(common, hdr, rx_status, rx_stats, decrypt_error,
|
|
sc->cur_chan->rxfilter)) {
|
|
spin_unlock_bh(&sc->chan_lock);
|
|
return -EINVAL;
|
|
}
|
|
spin_unlock_bh(&sc->chan_lock);
|
|
|
|
if (ath_is_mybeacon(common, hdr)) {
|
|
RX_STAT_INC(rx_beacons);
|
|
rx_stats->is_mybeacon = true;
|
|
}
|
|
|
|
/*
|
|
* This shouldn't happen, but have a safety check anyway.
|
|
*/
|
|
if (WARN_ON(!ah->curchan))
|
|
return -EINVAL;
|
|
|
|
if (ath9k_cmn_process_rate(common, hw, rx_stats, rx_status)) {
|
|
/*
|
|
* No valid hardware bitrate found -- we should not get here
|
|
* because hardware has already validated this frame as OK.
|
|
*/
|
|
ath_dbg(common, ANY, "unsupported hw bitrate detected 0x%02x using 1 Mbit\n",
|
|
rx_stats->rs_rate);
|
|
RX_STAT_INC(rx_rate_err);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (ath9k_is_chanctx_enabled()) {
|
|
if (rx_stats->is_mybeacon)
|
|
ath_chanctx_beacon_recv_ev(sc,
|
|
ATH_CHANCTX_EVENT_BEACON_RECEIVED);
|
|
}
|
|
|
|
ath9k_cmn_process_rssi(common, hw, rx_stats, rx_status);
|
|
|
|
rx_status->band = ah->curchan->chan->band;
|
|
rx_status->freq = ah->curchan->chan->center_freq;
|
|
rx_status->antenna = rx_stats->rs_antenna;
|
|
rx_status->flag |= RX_FLAG_MACTIME_END;
|
|
|
|
#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
|
|
if (ieee80211_is_data_present(hdr->frame_control) &&
|
|
!ieee80211_is_qos_nullfunc(hdr->frame_control))
|
|
sc->rx.num_pkts++;
|
|
#endif
|
|
|
|
return 0;
|
|
|
|
corrupt:
|
|
sc->rx.discard_next = rx_stats->rs_more;
|
|
return -EINVAL;
|
|
}
|
|
|
|
/*
|
|
* Run the LNA combining algorithm only in these cases:
|
|
*
|
|
* Standalone WLAN cards with both LNA/Antenna diversity
|
|
* enabled in the EEPROM.
|
|
*
|
|
* WLAN+BT cards which are in the supported card list
|
|
* in ath_pci_id_table and the user has loaded the
|
|
* driver with "bt_ant_diversity" set to true.
|
|
*/
|
|
static void ath9k_antenna_check(struct ath_softc *sc,
|
|
struct ath_rx_status *rs)
|
|
{
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
struct ath9k_hw_capabilities *pCap = &ah->caps;
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
|
|
if (!(ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB))
|
|
return;
|
|
|
|
/*
|
|
* Change the default rx antenna if rx diversity
|
|
* chooses the other antenna 3 times in a row.
|
|
*/
|
|
if (sc->rx.defant != rs->rs_antenna) {
|
|
if (++sc->rx.rxotherant >= 3)
|
|
ath_setdefantenna(sc, rs->rs_antenna);
|
|
} else {
|
|
sc->rx.rxotherant = 0;
|
|
}
|
|
|
|
if (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV) {
|
|
if (common->bt_ant_diversity)
|
|
ath_ant_comb_scan(sc, rs);
|
|
} else {
|
|
ath_ant_comb_scan(sc, rs);
|
|
}
|
|
}
|
|
|
|
static void ath9k_apply_ampdu_details(struct ath_softc *sc,
|
|
struct ath_rx_status *rs, struct ieee80211_rx_status *rxs)
|
|
{
|
|
if (rs->rs_isaggr) {
|
|
rxs->flag |= RX_FLAG_AMPDU_DETAILS | RX_FLAG_AMPDU_LAST_KNOWN;
|
|
|
|
rxs->ampdu_reference = sc->rx.ampdu_ref;
|
|
|
|
if (!rs->rs_moreaggr) {
|
|
rxs->flag |= RX_FLAG_AMPDU_IS_LAST;
|
|
sc->rx.ampdu_ref++;
|
|
}
|
|
|
|
if (rs->rs_flags & ATH9K_RX_DELIM_CRC_PRE)
|
|
rxs->flag |= RX_FLAG_AMPDU_DELIM_CRC_ERROR;
|
|
}
|
|
}
|
|
|
|
int ath_rx_tasklet(struct ath_softc *sc, int flush, bool hp)
|
|
{
|
|
struct ath_rxbuf *bf;
|
|
struct sk_buff *skb = NULL, *requeue_skb, *hdr_skb;
|
|
struct ieee80211_rx_status *rxs;
|
|
struct ath_hw *ah = sc->sc_ah;
|
|
struct ath_common *common = ath9k_hw_common(ah);
|
|
struct ieee80211_hw *hw = sc->hw;
|
|
int retval;
|
|
struct ath_rx_status rs;
|
|
enum ath9k_rx_qtype qtype;
|
|
bool edma = !!(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA);
|
|
int dma_type;
|
|
u64 tsf = 0;
|
|
unsigned long flags;
|
|
dma_addr_t new_buf_addr;
|
|
unsigned int budget = 512;
|
|
struct ieee80211_hdr *hdr;
|
|
|
|
if (edma)
|
|
dma_type = DMA_BIDIRECTIONAL;
|
|
else
|
|
dma_type = DMA_FROM_DEVICE;
|
|
|
|
qtype = hp ? ATH9K_RX_QUEUE_HP : ATH9K_RX_QUEUE_LP;
|
|
|
|
tsf = ath9k_hw_gettsf64(ah);
|
|
|
|
do {
|
|
bool decrypt_error = false;
|
|
|
|
memset(&rs, 0, sizeof(rs));
|
|
if (edma)
|
|
bf = ath_edma_get_next_rx_buf(sc, &rs, qtype);
|
|
else
|
|
bf = ath_get_next_rx_buf(sc, &rs);
|
|
|
|
if (!bf)
|
|
break;
|
|
|
|
skb = bf->bf_mpdu;
|
|
if (!skb)
|
|
continue;
|
|
|
|
/*
|
|
* Take frame header from the first fragment and RX status from
|
|
* the last one.
|
|
*/
|
|
if (sc->rx.frag)
|
|
hdr_skb = sc->rx.frag;
|
|
else
|
|
hdr_skb = skb;
|
|
|
|
rxs = IEEE80211_SKB_RXCB(hdr_skb);
|
|
memset(rxs, 0, sizeof(struct ieee80211_rx_status));
|
|
|
|
retval = ath9k_rx_skb_preprocess(sc, hdr_skb, &rs, rxs,
|
|
&decrypt_error, tsf);
|
|
if (retval)
|
|
goto requeue_drop_frag;
|
|
|
|
/* Ensure we always have an skb to requeue once we are done
|
|
* processing the current buffer's skb */
|
|
requeue_skb = ath_rxbuf_alloc(common, common->rx_bufsize, GFP_ATOMIC);
|
|
|
|
/* If there is no memory we ignore the current RX'd frame,
|
|
* tell hardware it can give us a new frame using the old
|
|
* skb and put it at the tail of the sc->rx.rxbuf list for
|
|
* processing. */
|
|
if (!requeue_skb) {
|
|
RX_STAT_INC(rx_oom_err);
|
|
goto requeue_drop_frag;
|
|
}
|
|
|
|
/* We will now give hardware our shiny new allocated skb */
|
|
new_buf_addr = dma_map_single(sc->dev, requeue_skb->data,
|
|
common->rx_bufsize, dma_type);
|
|
if (unlikely(dma_mapping_error(sc->dev, new_buf_addr))) {
|
|
dev_kfree_skb_any(requeue_skb);
|
|
goto requeue_drop_frag;
|
|
}
|
|
|
|
/* Unmap the frame */
|
|
dma_unmap_single(sc->dev, bf->bf_buf_addr,
|
|
common->rx_bufsize, dma_type);
|
|
|
|
bf->bf_mpdu = requeue_skb;
|
|
bf->bf_buf_addr = new_buf_addr;
|
|
|
|
skb_put(skb, rs.rs_datalen + ah->caps.rx_status_len);
|
|
if (ah->caps.rx_status_len)
|
|
skb_pull(skb, ah->caps.rx_status_len);
|
|
|
|
if (!rs.rs_more)
|
|
ath9k_cmn_rx_skb_postprocess(common, hdr_skb, &rs,
|
|
rxs, decrypt_error);
|
|
|
|
if (rs.rs_more) {
|
|
RX_STAT_INC(rx_frags);
|
|
/*
|
|
* rs_more indicates chained descriptors which can be
|
|
* used to link buffers together for a sort of
|
|
* scatter-gather operation.
|
|
*/
|
|
if (sc->rx.frag) {
|
|
/* too many fragments - cannot handle frame */
|
|
dev_kfree_skb_any(sc->rx.frag);
|
|
dev_kfree_skb_any(skb);
|
|
RX_STAT_INC(rx_too_many_frags_err);
|
|
skb = NULL;
|
|
}
|
|
sc->rx.frag = skb;
|
|
goto requeue;
|
|
}
|
|
|
|
if (sc->rx.frag) {
|
|
int space = skb->len - skb_tailroom(hdr_skb);
|
|
|
|
if (pskb_expand_head(hdr_skb, 0, space, GFP_ATOMIC) < 0) {
|
|
dev_kfree_skb(skb);
|
|
RX_STAT_INC(rx_oom_err);
|
|
goto requeue_drop_frag;
|
|
}
|
|
|
|
sc->rx.frag = NULL;
|
|
|
|
skb_copy_from_linear_data(skb, skb_put(hdr_skb, skb->len),
|
|
skb->len);
|
|
dev_kfree_skb_any(skb);
|
|
skb = hdr_skb;
|
|
}
|
|
|
|
if (rxs->flag & RX_FLAG_MMIC_STRIPPED)
|
|
skb_trim(skb, skb->len - 8);
|
|
|
|
spin_lock_irqsave(&sc->sc_pm_lock, flags);
|
|
if ((sc->ps_flags & (PS_WAIT_FOR_BEACON |
|
|
PS_WAIT_FOR_CAB |
|
|
PS_WAIT_FOR_PSPOLL_DATA)) ||
|
|
ath9k_check_auto_sleep(sc))
|
|
ath_rx_ps(sc, skb, rs.is_mybeacon);
|
|
spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
|
|
|
|
ath9k_antenna_check(sc, &rs);
|
|
ath9k_apply_ampdu_details(sc, &rs, rxs);
|
|
ath_debug_rate_stats(sc, &rs, skb);
|
|
|
|
hdr = (struct ieee80211_hdr *)skb->data;
|
|
if (ieee80211_is_ack(hdr->frame_control))
|
|
ath_dynack_sample_ack_ts(sc->sc_ah, skb, rs.rs_tstamp);
|
|
|
|
ieee80211_rx(hw, skb);
|
|
|
|
requeue_drop_frag:
|
|
if (sc->rx.frag) {
|
|
dev_kfree_skb_any(sc->rx.frag);
|
|
sc->rx.frag = NULL;
|
|
}
|
|
requeue:
|
|
list_add_tail(&bf->list, &sc->rx.rxbuf);
|
|
|
|
if (!edma) {
|
|
ath_rx_buf_relink(sc, bf, flush);
|
|
if (!flush)
|
|
ath9k_hw_rxena(ah);
|
|
} else if (!flush) {
|
|
ath_rx_edma_buf_link(sc, qtype);
|
|
}
|
|
|
|
if (!budget--)
|
|
break;
|
|
} while (1);
|
|
|
|
if (!(ah->imask & ATH9K_INT_RXEOL)) {
|
|
ah->imask |= (ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
|
|
ath9k_hw_set_interrupts(ah);
|
|
}
|
|
|
|
return 0;
|
|
}
|