Jack Xiao b8cb98cd3e drm/amdgpu/gfx10: fix programming of SC_HIZ_TILE_FIFO_SIZE field ... max fifo size is 128 and PA_SC_FIFO_SIZE[20:15]=SC_HIZ_TILE_FIFO_SIZE field is programmed in units of two entries, but 6 bits is insufficient to hold value 128/2 = 64, so set this field as 0 which is interpreted by the hardware as maximum physical fifo size(128). Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-07-18 14:17:59 -05:00
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acp	treewide: Add SPDX license identifier - Makefile/Kconfig	2019-05-21 10:50:46 +02:00
amdgpu	drm/amdgpu/gfx10: fix programming of SC_HIZ_TILE_FIFO_SIZE field	2019-07-18 14:17:59 -05:00
amdkfd	drm/amdkfd: Remove GWS from process during uninit	2019-07-17 13:34:31 -05:00
display	drm/amd/display: init res_pool dccg_ref, dchub_ref with xtalin_freq	2019-07-18 14:12:08 -05:00
include	drm/amdgpu/soc15: initialize reg base for navi14 (v2)	2019-07-18 14:17:58 -05:00
powerplay	drm/amd/powerplay: update vega20 driver if to fit latest SMU firmware	2019-07-17 13:34:30 -05:00