Bjorn Helgaas 0a8f41023e PCI: Move Apex Edge TPU class quirk to fix BAR assignment ... Some Google Apex Edge TPU devices have a class code of 0 (PCI_CLASS_NOT_DEFINED). This prevents the PCI core from assigning resources for the Apex BARs because __dev_sort_resources() ignores classless devices, host bridges, and IOAPICs. On x86, firmware typically assigns those resources, so this was not a problem. But on some architectures, firmware does *not* assign BARs, and since the PCI core didn't do it either, the Apex device didn't work correctly: apex 0000:01:00.0: can't enable device: BAR 0 [mem 0x00000000-0x00003fff 64bit pref] not claimed apex 0000:01:00.0: error enabling PCI device f390d08d8b ("staging: gasket: apex: fixup undefined PCI class") added a quirk to fix the class code, but it was in the apex driver, and if the driver was built as a module, it was too late to help. Move the quirk to the PCI core, where it will always run early enough that the PCI core will assign resources if necessary. Link: https://lore.kernel.org/r/CAEzXK1r0Er039iERnc2KJ4jn7ySNUOG9H=Ha8TD8XroVqiZjgg@mail.gmail.com Fixes: f390d08d8b ("staging: gasket: apex: fixup undefined PCI class") Reported-by: Luís Mendes <luis.p.mendes@gmail.com> Debugged-by: Luís Mendes <luis.p.mendes@gmail.com> Tested-by: Luis Mendes <luis.p.mendes@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Todd Poynor <toddpoynor@google.com>		2020-04-14 19:16:51 -05:00
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controller	pci-v5.7-changes	2020-04-03 14:25:02 -07:00
endpoint	PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSI-X table address	2020-04-02 17:57:10 +01:00
hotplug	powerpc updates for 5.7	2020-04-05 11:12:59 -07:00
pcie	pci-v5.7-changes	2020-04-03 14:25:02 -07:00
switch	pci/switchtec: Replace completion wait queue usage for poll	2020-03-21 16:00:20 +01:00
access.c
ats.c	PCI/ATS: Export symbols of PASID functions	2020-03-18 21:32:25 +00:00
bus.c
ecam.c
host-bridge.c
iov.c
irq.c
Kconfig
Makefile
mmap.c
msi.c
of.c
p2pdma.c	PCI/P2PDMA: Add Intel Sky Lake-E Root Ports B, C, D to the whitelist	2020-03-18 18:09:07 -05:00
pci-acpi.c	Merge branch 'pci/misc'	2020-04-02 14:26:38 -05:00
pci-bridge-emul.c	PCI: pci-bridge-emul: Use new constant PCI_STATUS_ERROR_BITS	2020-03-04 14:21:00 -08:00
pci-bridge-emul.h
pci-driver.c
pci-label.c
pci-mid.c	PCI: intel-mid: Convert to new X86 CPU match macros	2020-03-24 21:35:06 +01:00
pci-pf-stub.c
pci-stub.c
pci-sysfs.c	Merge branch 'pci/misc'	2020-04-02 14:26:38 -05:00
pci.c	pci-v5.7-changes	2020-04-03 14:25:02 -07:00
pci.h	Merge branch 'pci/enumeration'	2020-04-02 14:26:32 -05:00
probe.c	Merge branch 'pci/enumeration'	2020-04-02 14:26:32 -05:00
proc.c
quirks.c	PCI: Move Apex Edge TPU class quirk to fix BAR assignment	2020-04-14 19:16:51 -05:00
remove.c
rom.c	PCI: Use ioremap(), not phys_to_virt() for platform ROM	2020-03-30 09:52:23 -05:00
search.c
setup-bus.c	PCI: Add support for root bus sizing	2020-03-30 09:52:34 -05:00
setup-irq.c
setup-res.c
slot.c	PCI: Add pci_speed_string()	2020-03-10 14:05:33 -05:00
syscall.c
vc.c
vpd.c
xen-pcifront.c