Vineet Gupta b8a0330239 ARCv2: barriers ... ARCv2 based HS38 cores are weakly ordered and thus explicit barriers for kernel proper. SMP barrier is provided by DMB instruction which also guarantees local barrier hence used as backend of smp_*mb() as well as *mb() APIs Also hookup barriers into MMIO accessors to avoid ordering issues in IO Cc: Peter Zijlstra (Intel) <peterz@infradead.org> Reviewed-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Vineet Gupta <vgupta@synopsys.com>		2015-06-25 06:00:17 +05:30
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arcregs.h	ARCv2: MMUv4: cache programming model changes	2015-06-22 14:06:55 +05:30
asm-offsets.h
atomic.h	ARC: add smp barriers around atomics per Documentation/atomic_ops.txt	2015-06-25 06:00:16 +05:30
barrier.h	ARCv2: barriers	2015-06-25 06:00:17 +05:30
bitops.h	ARC: add smp barriers around atomics per Documentation/atomic_ops.txt	2015-06-25 06:00:16 +05:30
bug.h	ARC: BUG() dumps stack after @msg (@msg now same as in generic BUG))	2014-10-13 14:46:18 +05:30
cache.h	ARCv2: MMUv4: support aliasing icache config	2015-06-22 14:06:56 +05:30
cacheflush.h	ARC: fold ___flush_dcache_page into __flush_dcache_page	2015-05-19 11:27:13 +05:30
checksum.h
clk.h
cmpxchg.h	ARC: add smp barriers around atomics per Documentation/atomic_ops.txt	2015-06-25 06:00:16 +05:30
current.h	ARC: remove extraneous __KERNEL__ guards	2014-10-13 14:46:20 +05:30
delay.h	ARCv2: Adhere to Zero Delay loop restriction	2015-06-22 14:06:56 +05:30
disasm.h
dma-mapping.h	ARC: remove the unused platform helpers from dma mapping API	2015-06-19 18:09:23 +05:30
dma.h
elf.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
entry-arcv2.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
entry-compact.h	ARC: intc: split into ARCompact ISA specific, common bits	2015-06-19 18:09:40 +05:30
entry.h	ARCv2: STAR 9000808988: signals involving Delay Slot	2015-06-22 14:06:55 +05:30
exec.h
futex.h
io.h	ARCv2: barriers	2015-06-25 06:00:17 +05:30
irq.h	ARCv2: SMP: Support ARConnect (MCIP) for Inter-Core-Interrupts et al	2015-06-22 14:06:56 +05:30
irqflags-arcv2.h	ARCv2: STAR 9000814690: Really Re-enable interrupts to avoid deadlocks	2015-06-22 14:06:55 +05:30
irqflags-compact.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
irqflags.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
Kbuild	ARCv2: barriers	2015-06-25 06:00:17 +05:30
kdebug.h
kgdb.h	ARC: Update order of registers in KGDB to match GDB 7.5	2014-10-13 14:46:20 +05:30
kprobes.h
linkage.h
mach_desc.h
mcip.h	ARCv2: SMP: clocksource: Enable Global Real Time counter	2015-06-22 14:06:57 +05:30
mmu_context.h
mmu.h	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30
module.h
mutex.h
page.h
perf_event.h	ARC: perf: support cache hit/miss ratio	2015-04-20 18:27:34 +05:30
pgalloc.h
pgtable.h	ARCv2: MMUv4: TLB programming Model changes	2015-06-22 14:06:55 +05:30
processor.h	ARC: mm: document system mem map clearly	2015-06-19 18:09:29 +05:30
ptrace.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
sections.h
segment.h
serial.h	ARC: Dynamically determine BASE_BAUD from DeviceTree	2015-02-02 17:08:37 +05:30
setup.h	ARC: RIP @running_on_hw	2014-10-13 14:46:17 +05:30
shmparam.h
smp.h
spinlock_types.h
spinlock.h	ARC: add smp barriers around atomics per Documentation/atomic_ops.txt	2015-06-25 06:00:16 +05:30
stacktrace.h	ARC: Make arc_unwind_core accessible externally	2015-02-27 10:15:00 +05:30
string.h	ARC: remove extraneous __KERNEL__ guards	2014-10-13 14:46:20 +05:30
switch_to.h
syscall.h
syscalls.h	ARC: remove extraneous __KERNEL__ guards	2014-10-13 14:46:20 +05:30
thread_info.h	ARCv2: Support for ARCv2 ISA and HS38x cores	2015-06-22 14:06:55 +05:30
timex.h
tlb-mmu1.h
tlb.h
tlbflush.h
uaccess.h	ARCv2: Adhere to Zero Delay loop restriction	2015-06-22 14:06:56 +05:30
unaligned.h	ARC: rename kconfig option for unaligned emulation	2014-10-13 14:46:15 +05:30
unwind.h