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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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3a37298ada
The Versatile Express IOFPGA as shipped on VECD 5.0 (bitfiles v108/208 and v116/216) contains a modified version of the PL180 MMCI, with PeriphID Configuration value changed to 0x2. This version adds an optional "hardware flow control" feature. When enabled MMC card clock will be automatically disabled when FIFO is about to over/underflow and re-enabled once the host retrieved some data. This makes the controller immune to over/underrun errors caused by big interrupt handling latencies. This patch adds relevant device variant in the driver. Signed-off-by: Pawel Moll <pawel.moll@arm.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
217 lines
6.2 KiB
C
217 lines
6.2 KiB
C
/*
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* linux/drivers/mmc/host/mmci.h - ARM PrimeCell MMCI PL180/1 driver
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*
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* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#define MMCIPOWER 0x000
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#define MCI_PWR_OFF 0x00
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#define MCI_PWR_UP 0x02
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#define MCI_PWR_ON 0x03
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#define MCI_OD (1 << 6)
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#define MCI_ROD (1 << 7)
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#define MMCICLOCK 0x004
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#define MCI_CLK_ENABLE (1 << 8)
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#define MCI_CLK_PWRSAVE (1 << 9)
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#define MCI_CLK_BYPASS (1 << 10)
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#define MCI_4BIT_BUS (1 << 11)
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/*
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* 8bit wide buses, hardware flow contronl, negative edges and clock inversion
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* supported in ST Micro U300 and Ux500 versions
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*/
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#define MCI_ST_8BIT_BUS (1 << 12)
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#define MCI_ST_U300_HWFCEN (1 << 13)
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#define MCI_ST_UX500_NEG_EDGE (1 << 13)
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#define MCI_ST_UX500_HWFCEN (1 << 14)
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#define MCI_ST_UX500_CLK_INV (1 << 15)
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/* Modified PL180 on Versatile Express platform */
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#define MCI_ARM_HWFCEN (1 << 12)
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#define MMCIARGUMENT 0x008
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#define MMCICOMMAND 0x00c
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#define MCI_CPSM_RESPONSE (1 << 6)
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#define MCI_CPSM_LONGRSP (1 << 7)
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#define MCI_CPSM_INTERRUPT (1 << 8)
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#define MCI_CPSM_PENDING (1 << 9)
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#define MCI_CPSM_ENABLE (1 << 10)
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#define MCI_SDIO_SUSP (1 << 11)
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#define MCI_ENCMD_COMPL (1 << 12)
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#define MCI_NIEN (1 << 13)
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#define MCI_CE_ATACMD (1 << 14)
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#define MMCIRESPCMD 0x010
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#define MMCIRESPONSE0 0x014
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#define MMCIRESPONSE1 0x018
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#define MMCIRESPONSE2 0x01c
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#define MMCIRESPONSE3 0x020
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#define MMCIDATATIMER 0x024
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#define MMCIDATALENGTH 0x028
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#define MMCIDATACTRL 0x02c
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#define MCI_DPSM_ENABLE (1 << 0)
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#define MCI_DPSM_DIRECTION (1 << 1)
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#define MCI_DPSM_MODE (1 << 2)
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#define MCI_DPSM_DMAENABLE (1 << 3)
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#define MCI_DPSM_BLOCKSIZE (1 << 4)
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/* Control register extensions in the ST Micro U300 and Ux500 versions */
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#define MCI_ST_DPSM_RWSTART (1 << 8)
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#define MCI_ST_DPSM_RWSTOP (1 << 9)
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#define MCI_ST_DPSM_RWMOD (1 << 10)
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#define MCI_ST_DPSM_SDIOEN (1 << 11)
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/* Control register extensions in the ST Micro Ux500 versions */
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#define MCI_ST_DPSM_DMAREQCTL (1 << 12)
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#define MCI_ST_DPSM_DBOOTMODEEN (1 << 13)
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#define MCI_ST_DPSM_BUSYMODE (1 << 14)
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#define MCI_ST_DPSM_DDRMODE (1 << 15)
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#define MMCIDATACNT 0x030
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#define MMCISTATUS 0x034
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#define MCI_CMDCRCFAIL (1 << 0)
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#define MCI_DATACRCFAIL (1 << 1)
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#define MCI_CMDTIMEOUT (1 << 2)
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#define MCI_DATATIMEOUT (1 << 3)
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#define MCI_TXUNDERRUN (1 << 4)
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#define MCI_RXOVERRUN (1 << 5)
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#define MCI_CMDRESPEND (1 << 6)
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#define MCI_CMDSENT (1 << 7)
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#define MCI_DATAEND (1 << 8)
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#define MCI_STARTBITERR (1 << 9)
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#define MCI_DATABLOCKEND (1 << 10)
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#define MCI_CMDACTIVE (1 << 11)
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#define MCI_TXACTIVE (1 << 12)
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#define MCI_RXACTIVE (1 << 13)
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#define MCI_TXFIFOHALFEMPTY (1 << 14)
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#define MCI_RXFIFOHALFFULL (1 << 15)
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#define MCI_TXFIFOFULL (1 << 16)
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#define MCI_RXFIFOFULL (1 << 17)
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#define MCI_TXFIFOEMPTY (1 << 18)
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#define MCI_RXFIFOEMPTY (1 << 19)
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#define MCI_TXDATAAVLBL (1 << 20)
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#define MCI_RXDATAAVLBL (1 << 21)
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/* Extended status bits for the ST Micro variants */
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#define MCI_ST_SDIOIT (1 << 22)
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#define MCI_ST_CEATAEND (1 << 23)
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#define MMCICLEAR 0x038
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#define MCI_CMDCRCFAILCLR (1 << 0)
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#define MCI_DATACRCFAILCLR (1 << 1)
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#define MCI_CMDTIMEOUTCLR (1 << 2)
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#define MCI_DATATIMEOUTCLR (1 << 3)
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#define MCI_TXUNDERRUNCLR (1 << 4)
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#define MCI_RXOVERRUNCLR (1 << 5)
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#define MCI_CMDRESPENDCLR (1 << 6)
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#define MCI_CMDSENTCLR (1 << 7)
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#define MCI_DATAENDCLR (1 << 8)
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#define MCI_STARTBITERRCLR (1 << 9)
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#define MCI_DATABLOCKENDCLR (1 << 10)
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/* Extended status bits for the ST Micro variants */
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#define MCI_ST_SDIOITC (1 << 22)
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#define MCI_ST_CEATAENDC (1 << 23)
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#define MMCIMASK0 0x03c
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#define MCI_CMDCRCFAILMASK (1 << 0)
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#define MCI_DATACRCFAILMASK (1 << 1)
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#define MCI_CMDTIMEOUTMASK (1 << 2)
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#define MCI_DATATIMEOUTMASK (1 << 3)
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#define MCI_TXUNDERRUNMASK (1 << 4)
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#define MCI_RXOVERRUNMASK (1 << 5)
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#define MCI_CMDRESPENDMASK (1 << 6)
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#define MCI_CMDSENTMASK (1 << 7)
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#define MCI_DATAENDMASK (1 << 8)
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#define MCI_STARTBITERRMASK (1 << 9)
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#define MCI_DATABLOCKENDMASK (1 << 10)
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#define MCI_CMDACTIVEMASK (1 << 11)
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#define MCI_TXACTIVEMASK (1 << 12)
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#define MCI_RXACTIVEMASK (1 << 13)
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#define MCI_TXFIFOHALFEMPTYMASK (1 << 14)
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#define MCI_RXFIFOHALFFULLMASK (1 << 15)
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#define MCI_TXFIFOFULLMASK (1 << 16)
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#define MCI_RXFIFOFULLMASK (1 << 17)
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#define MCI_TXFIFOEMPTYMASK (1 << 18)
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#define MCI_RXFIFOEMPTYMASK (1 << 19)
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#define MCI_TXDATAAVLBLMASK (1 << 20)
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#define MCI_RXDATAAVLBLMASK (1 << 21)
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/* Extended status bits for the ST Micro variants */
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#define MCI_ST_SDIOITMASK (1 << 22)
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#define MCI_ST_CEATAENDMASK (1 << 23)
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#define MMCIMASK1 0x040
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#define MMCIFIFOCNT 0x048
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#define MMCIFIFO 0x080 /* to 0x0bc */
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#define MCI_IRQENABLE \
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(MCI_CMDCRCFAILMASK|MCI_DATACRCFAILMASK|MCI_CMDTIMEOUTMASK| \
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MCI_DATATIMEOUTMASK|MCI_TXUNDERRUNMASK|MCI_RXOVERRUNMASK| \
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MCI_CMDRESPENDMASK|MCI_CMDSENTMASK|MCI_STARTBITERRMASK)
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/* These interrupts are directed to IRQ1 when two IRQ lines are available */
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#define MCI_IRQ1MASK \
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(MCI_RXFIFOHALFFULLMASK | MCI_RXDATAAVLBLMASK | \
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MCI_TXFIFOHALFEMPTYMASK)
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#define NR_SG 128
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struct clk;
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struct variant_data;
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struct dma_chan;
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struct mmci_host_next {
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struct dma_async_tx_descriptor *dma_desc;
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struct dma_chan *dma_chan;
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s32 cookie;
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};
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struct mmci_host {
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phys_addr_t phybase;
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void __iomem *base;
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struct mmc_request *mrq;
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struct mmc_command *cmd;
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struct mmc_data *data;
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struct mmc_host *mmc;
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struct clk *clk;
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int gpio_cd;
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int gpio_wp;
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int gpio_cd_irq;
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bool singleirq;
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spinlock_t lock;
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unsigned int mclk;
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unsigned int cclk;
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u32 pwr_reg;
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u32 clk_reg;
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struct mmci_platform_data *plat;
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struct variant_data *variant;
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u8 hw_designer;
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u8 hw_revision:4;
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struct timer_list timer;
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unsigned int oldstat;
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/* pio stuff */
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struct sg_mapping_iter sg_miter;
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unsigned int size;
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/* pinctrl handles */
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struct pinctrl *pinctrl;
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struct pinctrl_state *pins_default;
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#ifdef CONFIG_DMA_ENGINE
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/* DMA stuff */
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struct dma_chan *dma_current;
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struct dma_chan *dma_rx_channel;
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struct dma_chan *dma_tx_channel;
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struct dma_async_tx_descriptor *dma_desc_current;
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struct mmci_host_next next_data;
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#define dma_inprogress(host) ((host)->dma_current)
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#else
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#define dma_inprogress(host) (0)
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#endif
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};
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