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b882964b37
Meson8m2 has a GP_PLL clock (similar to GP0_PLL on GXBB/GXL/GXM) which is used as input for the VPU clocks. The only supported frequency (based on Amlogic's vendor kernel sources) is 364MHz which is achieved using the following parameters: - input: XTAL (24MHz) - M = 182 - N = 3 - OD = 2 ^ 2 Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190324151104.18397-4-martin.blumenstingl@googlemail.com
163 lines
5.7 KiB
C
163 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* Copyright (c) 2016 BayLibre, Inc.
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* Michael Turquette <mturquette@baylibre.com>
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*/
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#ifndef __MESON8B_H
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#define __MESON8B_H
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/*
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* Clock controller register offsets
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*
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* Register offsets from the HardKernel[0] data sheet are listed in comment
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* blocks below. Those offsets must be multiplied by 4 before adding them to
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* the base address to get the right value
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*
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* [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
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*/
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#define HHI_GP_PLL_CNTL 0x40 /* 0x10 offset in data sheet */
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#define HHI_VIID_CLK_DIV 0x128 /* 0x4a offset in data sheet */
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#define HHI_VIID_CLK_CNTL 0x12c /* 0x4b offset in data sheet */
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#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet */
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#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet */
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#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet */
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#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet */
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#define HHI_GCLK_AO 0x154 /* 0x55 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL1 0x15c /* 0x57 offset in data sheet */
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#define HHI_VID_CLK_DIV 0x164 /* 0x59 offset in data sheet */
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#define HHI_MPEG_CLK_CNTL 0x174 /* 0x5d offset in data sheet */
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#define HHI_VID_CLK_CNTL 0x17c /* 0x5f offset in data sheet */
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#define HHI_VID_CLK_CNTL2 0x194 /* 0x65 offset in data sheet */
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#define HHI_VID_DIVIDER_CNTL 0x198 /* 0x66 offset in data sheet */
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#define HHI_SYS_CPU_CLK_CNTL0 0x19c /* 0x67 offset in data sheet */
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#define HHI_MALI_CLK_CNTL 0x1b0 /* 0x6c offset in data sheet */
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#define HHI_HDMI_CLK_CNTL 0x1cc /* 0x73 offset in data sheet */
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#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet */
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_SYS_PLL_CNTL 0x300 /* 0xc0 offset in data sheet */
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#define HHI_VID_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */
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#define HHI_VID_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */
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/*
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* MPLL register offeset taken from the S905 datasheet. Vendor kernel source
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* confirm these are the same for the S805.
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*/
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#define HHI_MPLL_CNTL 0x280 /* 0xa0 offset in data sheet */
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#define HHI_MPLL_CNTL2 0x284 /* 0xa1 offset in data sheet */
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#define HHI_MPLL_CNTL3 0x288 /* 0xa2 offset in data sheet */
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#define HHI_MPLL_CNTL4 0x28C /* 0xa3 offset in data sheet */
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#define HHI_MPLL_CNTL5 0x290 /* 0xa4 offset in data sheet */
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#define HHI_MPLL_CNTL6 0x294 /* 0xa5 offset in data sheet */
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#define HHI_MPLL_CNTL7 0x298 /* 0xa6 offset in data sheet */
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#define HHI_MPLL_CNTL8 0x29C /* 0xa7 offset in data sheet */
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#define HHI_MPLL_CNTL9 0x2A0 /* 0xa8 offset in data sheet */
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#define HHI_MPLL_CNTL10 0x2A4 /* 0xa9 offset in data sheet */
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/*
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* CLKID index values
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*
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* These indices are entirely contrived and do not map onto the hardware.
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* It has now been decided to expose everything by default in the DT header:
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* include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
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* to expose, such as the internal muxes and dividers of composite clocks,
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* will remain defined here.
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*/
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#define CLKID_MPLL0_DIV 96
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#define CLKID_MPLL1_DIV 97
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#define CLKID_MPLL2_DIV 98
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#define CLKID_CPU_IN_SEL 99
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#define CLKID_CPU_IN_DIV2 100
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#define CLKID_CPU_IN_DIV3 101
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#define CLKID_CPU_SCALE_DIV 102
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#define CLKID_CPU_SCALE_OUT_SEL 103
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#define CLKID_MPLL_PREDIV 104
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#define CLKID_FCLK_DIV2_DIV 105
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#define CLKID_FCLK_DIV3_DIV 106
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#define CLKID_FCLK_DIV4_DIV 107
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#define CLKID_FCLK_DIV5_DIV 108
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#define CLKID_FCLK_DIV7_DIV 109
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#define CLKID_NAND_SEL 110
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#define CLKID_NAND_DIV 111
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#define CLKID_PLL_FIXED_DCO 113
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#define CLKID_HDMI_PLL_DCO 114
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#define CLKID_PLL_SYS_DCO 115
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#define CLKID_CPU_CLK_DIV2 116
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#define CLKID_CPU_CLK_DIV3 117
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#define CLKID_CPU_CLK_DIV4 118
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#define CLKID_CPU_CLK_DIV5 119
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#define CLKID_CPU_CLK_DIV6 120
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#define CLKID_CPU_CLK_DIV7 121
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#define CLKID_CPU_CLK_DIV8 122
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#define CLKID_APB_SEL 123
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#define CLKID_PERIPH_SEL 125
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#define CLKID_AXI_SEL 127
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#define CLKID_L2_DRAM_SEL 129
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#define CLKID_HDMI_PLL_LVDS_OUT 131
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#define CLKID_HDMI_PLL_HDMI_OUT 132
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#define CLKID_VID_PLL_IN_SEL 133
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#define CLKID_VID_PLL_IN_EN 134
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#define CLKID_VID_PLL_PRE_DIV 135
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#define CLKID_VID_PLL_POST_DIV 136
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#define CLKID_VID_PLL_FINAL_DIV 137
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#define CLKID_VCLK_IN_SEL 138
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#define CLKID_VCLK_IN_EN 139
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#define CLKID_VCLK_DIV1 140
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#define CLKID_VCLK_DIV2_DIV 141
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#define CLKID_VCLK_DIV2 142
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#define CLKID_VCLK_DIV4_DIV 143
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#define CLKID_VCLK_DIV4 144
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#define CLKID_VCLK_DIV6_DIV 145
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#define CLKID_VCLK_DIV6 146
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#define CLKID_VCLK_DIV12_DIV 147
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#define CLKID_VCLK_DIV12 148
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#define CLKID_VCLK2_IN_SEL 149
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#define CLKID_VCLK2_IN_EN 150
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#define CLKID_VCLK2_DIV1 151
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#define CLKID_VCLK2_DIV2_DIV 152
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#define CLKID_VCLK2_DIV2 153
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#define CLKID_VCLK2_DIV4_DIV 154
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#define CLKID_VCLK2_DIV4 155
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#define CLKID_VCLK2_DIV6_DIV 156
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#define CLKID_VCLK2_DIV6 157
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#define CLKID_VCLK2_DIV12_DIV 158
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#define CLKID_VCLK2_DIV12 159
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#define CLKID_CTS_ENCT_SEL 160
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#define CLKID_CTS_ENCT 161
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#define CLKID_CTS_ENCP_SEL 162
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#define CLKID_CTS_ENCP 163
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#define CLKID_CTS_ENCI_SEL 164
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#define CLKID_CTS_ENCI 165
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#define CLKID_HDMI_TX_PIXEL_SEL 166
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#define CLKID_HDMI_TX_PIXEL 167
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#define CLKID_CTS_ENCL_SEL 168
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#define CLKID_CTS_ENCL 169
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#define CLKID_CTS_VDAC0_SEL 170
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#define CLKID_CTS_VDAC0 171
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#define CLKID_HDMI_SYS_SEL 172
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#define CLKID_HDMI_SYS_DIV 173
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#define CLKID_HDMI_SYS 174
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#define CLKID_MALI_0_SEL 175
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#define CLKID_MALI_0_DIV 176
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#define CLKID_MALI_0 177
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#define CLKID_MALI_1_SEL 178
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#define CLKID_MALI_1_DIV 179
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#define CLKID_MALI_1 180
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#define CLKID_GP_PLL_DCO 181
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#define CLKID_GP_PLL 182
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#define CLK_NR_CLKS 183
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/*
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* include the CLKID and RESETID that have
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* been made part of the stable DT binding
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*/
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
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#endif /* __MESON8B_H */
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