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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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107177b14d
ARC HS Cores support configurable multiple interrupt priorities of upto
16 levels. In commit dec2b2849c ("ARCv2: intc: Allow interruption by
lowest priority interrupt") we switched to 15 which seems a bit
excessive given that there would be rare hardware implementing so many
preemption levels AND running Linux. It would seem that 2 levels will be
more common so switch to 1 as the default priority level. This will be
the "lower" priority level saving 0 for implementing NMI style support.
This scheme also works in systems with more than 2 prioity levels as
well.
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
176 lines
3.6 KiB
C
176 lines
3.6 KiB
C
/*
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* Copyright (C) 2014-15 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_IRQFLAGS_ARCV2_H
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#define __ASM_IRQFLAGS_ARCV2_H
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#include <asm/arcregs.h>
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/* status32 Bits */
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#define STATUS_AD_BIT 19 /* Disable Align chk: core supports non-aligned */
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#define STATUS_IE_BIT 31
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#define STATUS_AD_MASK (1<<STATUS_AD_BIT)
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#define STATUS_IE_MASK (1<<STATUS_IE_BIT)
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/* status32 Bits as encoded/expected by CLRI/SETI */
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#define CLRI_STATUS_IE_BIT 4
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#define CLRI_STATUS_E_MASK 0xF
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#define CLRI_STATUS_IE_MASK (1 << CLRI_STATUS_IE_BIT)
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#define AUX_USER_SP 0x00D
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#define AUX_IRQ_CTRL 0x00E
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#define AUX_IRQ_ACT 0x043 /* Active Intr across all levels */
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#define AUX_IRQ_LVL_PEND 0x200 /* Pending Intr across all levels */
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#define AUX_IRQ_HINT 0x201 /* For generating Soft Interrupts */
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#define AUX_IRQ_PRIORITY 0x206
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#define ICAUSE 0x40a
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#define AUX_IRQ_SELECT 0x40b
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#define AUX_IRQ_ENABLE 0x40c
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/* Was Intr taken in User Mode */
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#define AUX_IRQ_ACT_BIT_U 31
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/*
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* Hardware supports 16 priorities (0 highest, 15 lowest)
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* Linux by default runs at 1, priority 0 reserved for NMI style interrupts
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*/
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#define ARCV2_IRQ_DEF_PRIO 1
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/* seed value for status register */
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#define ISA_INIT_STATUS_BITS (STATUS_IE_MASK | STATUS_AD_MASK | \
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(ARCV2_IRQ_DEF_PRIO << 1))
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/* SLEEP needs default irq priority (<=) which can interrupt the doze */
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#define ISA_SLEEP_ARG (0x10 | ARCV2_IRQ_DEF_PRIO)
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#ifndef __ASSEMBLY__
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/*
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* Save IRQ state and disable IRQs
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*/
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static inline long arch_local_irq_save(void)
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{
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unsigned long flags;
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__asm__ __volatile__(" clri %0 \n" : "=r" (flags) : : "memory");
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return flags;
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}
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/*
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* restore saved IRQ state
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*/
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static inline void arch_local_irq_restore(unsigned long flags)
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{
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__asm__ __volatile__(" seti %0 \n" : : "r" (flags) : "memory");
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}
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/*
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* Unconditionally Enable IRQs
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*/
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static inline void arch_local_irq_enable(void)
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{
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unsigned int irqact = read_aux_reg(AUX_IRQ_ACT);
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if (irqact & 0xffff)
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write_aux_reg(AUX_IRQ_ACT, irqact & ~0xffff);
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__asm__ __volatile__(" seti \n" : : : "memory");
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}
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/*
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* Unconditionally Disable IRQs
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*/
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static inline void arch_local_irq_disable(void)
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{
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__asm__ __volatile__(" clri \n" : : : "memory");
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}
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/*
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* save IRQ state
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*/
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static inline long arch_local_save_flags(void)
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{
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unsigned long temp;
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__asm__ __volatile__(
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" lr %0, [status32] \n"
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: "=&r"(temp)
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:
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: "memory");
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/* To be compatible with irq_save()/irq_restore()
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* encode the irq bits as expected by CLRI/SETI
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* (this was needed to make CONFIG_TRACE_IRQFLAGS work)
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*/
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temp = (1 << 5) |
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((!!(temp & STATUS_IE_MASK)) << CLRI_STATUS_IE_BIT) |
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((temp >> 1) & CLRI_STATUS_E_MASK);
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return temp;
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}
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/*
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* Query IRQ state
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*/
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static inline int arch_irqs_disabled_flags(unsigned long flags)
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{
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return !(flags & CLRI_STATUS_IE_MASK);
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}
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static inline int arch_irqs_disabled(void)
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{
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return arch_irqs_disabled_flags(arch_local_save_flags());
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}
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static inline void arc_softirq_trigger(int irq)
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{
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write_aux_reg(AUX_IRQ_HINT, irq);
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}
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static inline void arc_softirq_clear(int irq)
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{
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write_aux_reg(AUX_IRQ_HINT, 0);
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}
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#else
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#ifdef CONFIG_TRACE_IRQFLAGS
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.macro TRACE_ASM_IRQ_DISABLE
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bl trace_hardirqs_off
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.endm
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.macro TRACE_ASM_IRQ_ENABLE
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bl trace_hardirqs_on
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.endm
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#else
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.macro TRACE_ASM_IRQ_DISABLE
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.endm
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.macro TRACE_ASM_IRQ_ENABLE
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.endm
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#endif
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.macro IRQ_DISABLE scratch
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clri
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TRACE_ASM_IRQ_DISABLE
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.endm
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.macro IRQ_ENABLE scratch
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TRACE_ASM_IRQ_ENABLE
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seti
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.endm
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#endif /* __ASSEMBLY__ */
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#endif
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