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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e785060ea3
- Adding some of the definitions missing in unipro.h, including power enumeration. - Read Modify Write Line helper function - Indication for the type of suspend Signed-off-by: Dolev Raviv <draviv@codeaurora.org> Signed-off-by: Subhash Jadavani <subhashj@codeaurora.org> Signed-off-by: Yaniv Gardi <ygardi@codeaurora.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
208 lines
5.7 KiB
C
208 lines
5.7 KiB
C
/*
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* drivers/scsi/ufs/unipro.h
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*
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* Copyright (C) 2013 Samsung Electronics Co., Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#ifndef _UNIPRO_H_
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#define _UNIPRO_H_
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/*
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* M-TX Configuration Attributes
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*/
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#define TX_MODE 0x0021
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#define TX_HSRATE_SERIES 0x0022
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#define TX_HSGEAR 0x0023
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#define TX_PWMGEAR 0x0024
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#define TX_AMPLITUDE 0x0025
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#define TX_HS_SLEWRATE 0x0026
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#define TX_SYNC_SOURCE 0x0027
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#define TX_HS_SYNC_LENGTH 0x0028
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#define TX_HS_PREPARE_LENGTH 0x0029
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#define TX_LS_PREPARE_LENGTH 0x002A
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#define TX_HIBERN8_CONTROL 0x002B
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#define TX_LCC_ENABLE 0x002C
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#define TX_PWM_BURST_CLOSURE_EXTENSION 0x002D
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#define TX_BYPASS_8B10B_ENABLE 0x002E
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#define TX_DRIVER_POLARITY 0x002F
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#define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE 0x0030
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#define TX_LS_TERMINATED_LINE_DRIVE_ENABLE 0x0031
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#define TX_LCC_SEQUENCER 0x0032
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#define TX_MIN_ACTIVATETIME 0x0033
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#define TX_PWM_G6_G7_SYNC_LENGTH 0x0034
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/*
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* M-RX Configuration Attributes
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*/
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#define RX_MODE 0x00A1
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#define RX_HSRATE_SERIES 0x00A2
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#define RX_HSGEAR 0x00A3
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#define RX_PWMGEAR 0x00A4
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#define RX_LS_TERMINATED_ENABLE 0x00A5
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#define RX_HS_UNTERMINATED_ENABLE 0x00A6
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#define RX_ENTER_HIBERN8 0x00A7
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#define RX_BYPASS_8B10B_ENABLE 0x00A8
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#define RX_TERMINATION_FORCE_ENABLE 0x0089
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#define is_mphy_tx_attr(attr) (attr < RX_MODE)
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/*
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* PHY Adpater attributes
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*/
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#define PA_ACTIVETXDATALANES 0x1560
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#define PA_ACTIVERXDATALANES 0x1580
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#define PA_TXTRAILINGCLOCKS 0x1564
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#define PA_PHY_TYPE 0x1500
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#define PA_AVAILTXDATALANES 0x1520
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#define PA_AVAILRXDATALANES 0x1540
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#define PA_MINRXTRAILINGCLOCKS 0x1543
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#define PA_TXPWRSTATUS 0x1567
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#define PA_RXPWRSTATUS 0x1582
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#define PA_TXFORCECLOCK 0x1562
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#define PA_TXPWRMODE 0x1563
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#define PA_LEGACYDPHYESCDL 0x1570
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#define PA_MAXTXSPEEDFAST 0x1521
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#define PA_MAXTXSPEEDSLOW 0x1522
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#define PA_MAXRXSPEEDFAST 0x1541
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#define PA_MAXRXSPEEDSLOW 0x1542
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#define PA_TXLINKSTARTUPHS 0x1544
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#define PA_TXSPEEDFAST 0x1565
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#define PA_TXSPEEDSLOW 0x1566
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#define PA_REMOTEVERINFO 0x15A0
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#define PA_TXGEAR 0x1568
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#define PA_TXTERMINATION 0x1569
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#define PA_HSSERIES 0x156A
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#define PA_PWRMODE 0x1571
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#define PA_RXGEAR 0x1583
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#define PA_RXTERMINATION 0x1584
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#define PA_MAXRXPWMGEAR 0x1586
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#define PA_MAXRXHSGEAR 0x1587
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#define PA_RXHSUNTERMCAP 0x15A5
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#define PA_RXLSTERMCAP 0x15A6
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#define PA_PACPREQTIMEOUT 0x1590
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#define PA_PACPREQEOBTIMEOUT 0x1591
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#define PA_HIBERN8TIME 0x15A7
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#define PA_LOCALVERINFO 0x15A9
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#define PA_TACTIVATE 0x15A8
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#define PA_PACPFRAMECOUNT 0x15C0
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#define PA_PACPERRORCOUNT 0x15C1
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#define PA_PHYTESTCONTROL 0x15C2
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#define PA_PWRMODEUSERDATA0 0x15B0
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#define PA_PWRMODEUSERDATA1 0x15B1
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#define PA_PWRMODEUSERDATA2 0x15B2
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#define PA_PWRMODEUSERDATA3 0x15B3
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#define PA_PWRMODEUSERDATA4 0x15B4
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#define PA_PWRMODEUSERDATA5 0x15B5
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#define PA_PWRMODEUSERDATA6 0x15B6
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#define PA_PWRMODEUSERDATA7 0x15B7
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#define PA_PWRMODEUSERDATA8 0x15B8
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#define PA_PWRMODEUSERDATA9 0x15B9
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#define PA_PWRMODEUSERDATA10 0x15BA
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#define PA_PWRMODEUSERDATA11 0x15BB
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#define PA_CONNECTEDTXDATALANES 0x1561
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#define PA_CONNECTEDRXDATALANES 0x1581
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#define PA_LOGICALLANEMAP 0x15A1
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#define PA_SLEEPNOCONFIGTIME 0x15A2
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#define PA_STALLNOCONFIGTIME 0x15A3
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#define PA_SAVECONFIGTIME 0x15A4
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/* PA power modes */
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enum {
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FAST_MODE = 1,
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SLOW_MODE = 2,
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FASTAUTO_MODE = 4,
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SLOWAUTO_MODE = 5,
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UNCHANGED = 7,
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};
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/* PA TX/RX Frequency Series */
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enum {
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PA_HS_MODE_A = 1,
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PA_HS_MODE_B = 2,
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};
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enum ufs_pwm_gear_tag {
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UFS_PWM_DONT_CHANGE, /* Don't change Gear */
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UFS_PWM_G1, /* PWM Gear 1 (default for reset) */
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UFS_PWM_G2, /* PWM Gear 2 */
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UFS_PWM_G3, /* PWM Gear 3 */
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UFS_PWM_G4, /* PWM Gear 4 */
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UFS_PWM_G5, /* PWM Gear 5 */
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UFS_PWM_G6, /* PWM Gear 6 */
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UFS_PWM_G7, /* PWM Gear 7 */
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};
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enum ufs_hs_gear_tag {
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UFS_HS_DONT_CHANGE, /* Don't change Gear */
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UFS_HS_G1, /* HS Gear 1 (default for reset) */
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UFS_HS_G2, /* HS Gear 2 */
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UFS_HS_G3, /* HS Gear 3 */
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};
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/*
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* Data Link Layer Attributes
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*/
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#define DL_TC0TXFCTHRESHOLD 0x2040
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#define DL_FC0PROTTIMEOUTVAL 0x2041
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#define DL_TC0REPLAYTIMEOUTVAL 0x2042
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#define DL_AFC0REQTIMEOUTVAL 0x2043
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#define DL_AFC0CREDITTHRESHOLD 0x2044
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#define DL_TC0OUTACKTHRESHOLD 0x2045
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#define DL_TC1TXFCTHRESHOLD 0x2060
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#define DL_FC1PROTTIMEOUTVAL 0x2061
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#define DL_TC1REPLAYTIMEOUTVAL 0x2062
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#define DL_AFC1REQTIMEOUTVAL 0x2063
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#define DL_AFC1CREDITTHRESHOLD 0x2064
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#define DL_TC1OUTACKTHRESHOLD 0x2065
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#define DL_TXPREEMPTIONCAP 0x2000
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#define DL_TC0TXMAXSDUSIZE 0x2001
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#define DL_TC0RXINITCREDITVAL 0x2002
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#define DL_TC0TXBUFFERSIZE 0x2005
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#define DL_PEERTC0PRESENT 0x2046
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#define DL_PEERTC0RXINITCREVAL 0x2047
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#define DL_TC1TXMAXSDUSIZE 0x2003
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#define DL_TC1RXINITCREDITVAL 0x2004
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#define DL_TC1TXBUFFERSIZE 0x2006
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#define DL_PEERTC1PRESENT 0x2066
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#define DL_PEERTC1RXINITCREVAL 0x2067
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/*
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* Network Layer Attributes
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*/
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#define N_DEVICEID 0x3000
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#define N_DEVICEID_VALID 0x3001
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#define N_TC0TXMAXSDUSIZE 0x3020
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#define N_TC1TXMAXSDUSIZE 0x3021
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/*
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* Transport Layer Attributes
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*/
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#define T_NUMCPORTS 0x4000
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#define T_NUMTESTFEATURES 0x4001
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#define T_CONNECTIONSTATE 0x4020
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#define T_PEERDEVICEID 0x4021
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#define T_PEERCPORTID 0x4022
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#define T_TRAFFICCLASS 0x4023
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#define T_PROTOCOLID 0x4024
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#define T_CPORTFLAGS 0x4025
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#define T_TXTOKENVALUE 0x4026
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#define T_RXTOKENVALUE 0x4027
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#define T_LOCALBUFFERSPACE 0x4028
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#define T_PEERBUFFERSPACE 0x4029
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#define T_CREDITSTOSEND 0x402A
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#define T_CPORTMODE 0x402B
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#define T_TC0TXMAXSDUSIZE 0x4060
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#define T_TC1TXMAXSDUSIZE 0x4061
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/* Boolean attribute values */
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enum {
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FALSE = 0,
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TRUE,
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};
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#endif /* _UNIPRO_H_ */
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