mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b8422dcb86
Add wl18xx-specific HW initialization operation and create acx.[ch] files to support that. Signed-off-by: Luciano Coelho <coelho@ti.com> Signed-off-by: Arik Nemtsov <arik@wizery.com>
579 lines
18 KiB
C
579 lines
18 KiB
C
/*
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* This file is part of wl18xx
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*
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* Copyright (C) 2011 Texas Instruments
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
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* 02110-1301 USA
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*
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*/
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "../wlcore/wlcore.h"
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#include "../wlcore/debug.h"
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#include "../wlcore/io.h"
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#include "../wlcore/acx.h"
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#include "../wlcore/tx.h"
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#include "../wlcore/rx.h"
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#include "../wlcore/io.h"
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#include "../wlcore/boot.h"
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#include "reg.h"
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#include "conf.h"
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#include "acx.h"
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#include "tx.h"
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#include "wl18xx.h"
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static const u8 wl18xx_rate_to_idx_2ghz[] = {
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/* MCS rates are used only with 11n */
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15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
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14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
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13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
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12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
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11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
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10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
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9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
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8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
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7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
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6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
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5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
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4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
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3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
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2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
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1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
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0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
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11, /* WL18XX_CONF_HW_RXTX_RATE_54 */
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10, /* WL18XX_CONF_HW_RXTX_RATE_48 */
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9, /* WL18XX_CONF_HW_RXTX_RATE_36 */
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8, /* WL18XX_CONF_HW_RXTX_RATE_24 */
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/* TI-specific rate */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
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7, /* WL18XX_CONF_HW_RXTX_RATE_18 */
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6, /* WL18XX_CONF_HW_RXTX_RATE_12 */
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3, /* WL18XX_CONF_HW_RXTX_RATE_11 */
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5, /* WL18XX_CONF_HW_RXTX_RATE_9 */
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4, /* WL18XX_CONF_HW_RXTX_RATE_6 */
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2, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
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1, /* WL18XX_CONF_HW_RXTX_RATE_2 */
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0 /* WL18XX_CONF_HW_RXTX_RATE_1 */
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};
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static const u8 wl18xx_rate_to_idx_5ghz[] = {
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/* MCS rates are used only with 11n */
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15, /* WL18XX_CONF_HW_RXTX_RATE_MCS15 */
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14, /* WL18XX_CONF_HW_RXTX_RATE_MCS14 */
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13, /* WL18XX_CONF_HW_RXTX_RATE_MCS13 */
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12, /* WL18XX_CONF_HW_RXTX_RATE_MCS12 */
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11, /* WL18XX_CONF_HW_RXTX_RATE_MCS11 */
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10, /* WL18XX_CONF_HW_RXTX_RATE_MCS10 */
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9, /* WL18XX_CONF_HW_RXTX_RATE_MCS9 */
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8, /* WL18XX_CONF_HW_RXTX_RATE_MCS8 */
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7, /* WL18XX_CONF_HW_RXTX_RATE_MCS7 */
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6, /* WL18XX_CONF_HW_RXTX_RATE_MCS6 */
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5, /* WL18XX_CONF_HW_RXTX_RATE_MCS5 */
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4, /* WL18XX_CONF_HW_RXTX_RATE_MCS4 */
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3, /* WL18XX_CONF_HW_RXTX_RATE_MCS3 */
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2, /* WL18XX_CONF_HW_RXTX_RATE_MCS2 */
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1, /* WL18XX_CONF_HW_RXTX_RATE_MCS1 */
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0, /* WL18XX_CONF_HW_RXTX_RATE_MCS0 */
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7, /* WL18XX_CONF_HW_RXTX_RATE_54 */
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6, /* WL18XX_CONF_HW_RXTX_RATE_48 */
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5, /* WL18XX_CONF_HW_RXTX_RATE_36 */
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4, /* WL18XX_CONF_HW_RXTX_RATE_24 */
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/* TI-specific rate */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_22 */
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3, /* WL18XX_CONF_HW_RXTX_RATE_18 */
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2, /* WL18XX_CONF_HW_RXTX_RATE_12 */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_11 */
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1, /* WL18XX_CONF_HW_RXTX_RATE_9 */
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0, /* WL18XX_CONF_HW_RXTX_RATE_6 */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_5_5 */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_2 */
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CONF_HW_RXTX_RATE_UNSUPPORTED, /* WL18XX_CONF_HW_RXTX_RATE_1 */
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};
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static const u8 *wl18xx_band_rate_to_idx[] = {
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[IEEE80211_BAND_2GHZ] = wl18xx_rate_to_idx_2ghz,
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[IEEE80211_BAND_5GHZ] = wl18xx_rate_to_idx_5ghz
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};
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enum wl18xx_hw_rates {
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WL18XX_CONF_HW_RXTX_RATE_MCS15 = 0,
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WL18XX_CONF_HW_RXTX_RATE_MCS14,
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WL18XX_CONF_HW_RXTX_RATE_MCS13,
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WL18XX_CONF_HW_RXTX_RATE_MCS12,
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WL18XX_CONF_HW_RXTX_RATE_MCS11,
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WL18XX_CONF_HW_RXTX_RATE_MCS10,
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WL18XX_CONF_HW_RXTX_RATE_MCS9,
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WL18XX_CONF_HW_RXTX_RATE_MCS8,
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WL18XX_CONF_HW_RXTX_RATE_MCS7,
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WL18XX_CONF_HW_RXTX_RATE_MCS6,
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WL18XX_CONF_HW_RXTX_RATE_MCS5,
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WL18XX_CONF_HW_RXTX_RATE_MCS4,
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WL18XX_CONF_HW_RXTX_RATE_MCS3,
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WL18XX_CONF_HW_RXTX_RATE_MCS2,
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WL18XX_CONF_HW_RXTX_RATE_MCS1,
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WL18XX_CONF_HW_RXTX_RATE_MCS0,
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WL18XX_CONF_HW_RXTX_RATE_54,
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WL18XX_CONF_HW_RXTX_RATE_48,
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WL18XX_CONF_HW_RXTX_RATE_36,
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WL18XX_CONF_HW_RXTX_RATE_24,
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WL18XX_CONF_HW_RXTX_RATE_22,
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WL18XX_CONF_HW_RXTX_RATE_18,
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WL18XX_CONF_HW_RXTX_RATE_12,
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WL18XX_CONF_HW_RXTX_RATE_11,
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WL18XX_CONF_HW_RXTX_RATE_9,
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WL18XX_CONF_HW_RXTX_RATE_6,
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WL18XX_CONF_HW_RXTX_RATE_5_5,
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WL18XX_CONF_HW_RXTX_RATE_2,
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WL18XX_CONF_HW_RXTX_RATE_1,
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WL18XX_CONF_HW_RXTX_RATE_MAX,
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};
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static struct wl18xx_conf wl18xx_default_conf = {
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.phy = {
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.phy_standalone = 0x00,
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.primary_clock_setting_time = 0x05,
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.clock_valid_on_wake_up = 0x00,
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.secondary_clock_setting_time = 0x05,
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.rdl = 0x01,
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.auto_detect = 0x00,
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.dedicated_fem = FEM_NONE,
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.low_band_component = COMPONENT_2_WAY_SWITCH,
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.low_band_component_type = 0x05,
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.high_band_component = COMPONENT_2_WAY_SWITCH,
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.high_band_component_type = 0x09,
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.number_of_assembled_ant2_4 = 0x01,
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.number_of_assembled_ant5 = 0x01,
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.external_pa_dc2dc = 0x00,
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.tcxo_ldo_voltage = 0x00,
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.xtal_itrim_val = 0x04,
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.srf_state = 0x00,
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.io_configuration = 0x01,
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.sdio_configuration = 0x00,
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.settings = 0x00,
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.enable_clpc = 0x00,
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.enable_tx_low_pwr_on_siso_rdl = 0x00,
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.rx_profile = 0x00,
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},
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};
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static const struct wlcore_partition_set wl18xx_ptable[PART_TABLE_LEN] = {
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[PART_TOP_PRCM_ELP_SOC] = {
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.mem = { .start = 0x00A02000, .size = 0x00010000 },
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.reg = { .start = 0x00807000, .size = 0x00005000 },
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.mem2 = { .start = 0x00800000, .size = 0x0000B000 },
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.mem3 = { .start = 0x00000000, .size = 0x00000000 },
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},
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[PART_DOWN] = {
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.mem = { .start = 0x00000000, .size = 0x00014000 },
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.reg = { .start = 0x00810000, .size = 0x0000BFFF },
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.mem2 = { .start = 0x00000000, .size = 0x00000000 },
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.mem3 = { .start = 0x00000000, .size = 0x00000000 },
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},
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[PART_BOOT] = {
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.mem = { .start = 0x00700000, .size = 0x0000030c },
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.reg = { .start = 0x00802000, .size = 0x00014578 },
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.mem2 = { .start = 0x00B00404, .size = 0x00001000 },
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.mem3 = { .start = 0x00C00000, .size = 0x00000400 },
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},
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[PART_WORK] = {
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.mem = { .start = 0x00800000, .size = 0x000050FC },
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.reg = { .start = 0x00B00404, .size = 0x00001000 },
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.mem2 = { .start = 0x00C00000, .size = 0x00000400 },
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.mem3 = { .start = 0x00000000, .size = 0x00000000 },
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},
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[PART_PHY_INIT] = {
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/* TODO: use the phy_conf struct size here */
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.mem = { .start = 0x80926000, .size = 252 },
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.reg = { .start = 0x00000000, .size = 0x00000000 },
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.mem2 = { .start = 0x00000000, .size = 0x00000000 },
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.mem3 = { .start = 0x00000000, .size = 0x00000000 },
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},
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};
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static const int wl18xx_rtable[REG_TABLE_LEN] = {
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[REG_ECPU_CONTROL] = WL18XX_REG_ECPU_CONTROL,
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[REG_INTERRUPT_NO_CLEAR] = WL18XX_REG_INTERRUPT_NO_CLEAR,
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[REG_INTERRUPT_ACK] = WL18XX_REG_INTERRUPT_ACK,
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[REG_COMMAND_MAILBOX_PTR] = WL18XX_REG_COMMAND_MAILBOX_PTR,
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[REG_EVENT_MAILBOX_PTR] = WL18XX_REG_EVENT_MAILBOX_PTR,
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[REG_INTERRUPT_TRIG] = WL18XX_REG_INTERRUPT_TRIG_H,
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[REG_INTERRUPT_MASK] = WL18XX_REG_INTERRUPT_MASK,
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[REG_PC_ON_RECOVERY] = 0, /* TODO: where is the PC? */
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[REG_CHIP_ID_B] = WL18XX_REG_CHIP_ID_B,
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[REG_CMD_MBOX_ADDRESS] = WL18XX_CMD_MBOX_ADDRESS,
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/* data access memory addresses, used with partition translation */
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[REG_SLV_MEM_DATA] = WL18XX_SLV_MEM_DATA,
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[REG_SLV_REG_DATA] = WL18XX_SLV_REG_DATA,
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/* raw data access memory addresses */
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[REG_RAW_FW_STATUS_ADDR] = WL18XX_FW_STATUS_ADDR,
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};
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/* TODO: maybe move to a new header file? */
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#define WL18XX_FW_NAME "ti-connectivity/wl18xx-fw.bin"
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static int wl18xx_identify_chip(struct wl1271 *wl)
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{
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int ret = 0;
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switch (wl->chip.id) {
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case CHIP_ID_185x_PG10:
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wl1271_debug(DEBUG_BOOT, "chip id 0x%x (185x PG10)",
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wl->chip.id);
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wl->sr_fw_name = WL18XX_FW_NAME;
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wl->quirks |= WLCORE_QUIRK_NO_ELP |
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WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN;
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/* TODO: need to blocksize alignment for RX/TX separately? */
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break;
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default:
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wl1271_warning("unsupported chip id: 0x%x", wl->chip.id);
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ret = -ENODEV;
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goto out;
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}
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out:
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return ret;
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}
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static void wl18xx_set_clk(struct wl1271 *wl)
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{
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/*
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* TODO: this is hardcoded just for DVP/EVB, fix according to
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* new unified_drv.
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*/
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wl1271_write32(wl, WL18XX_SCR_PAD2, 0xB3);
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wlcore_set_partition(wl, &wl->ptable[PART_TOP_PRCM_ELP_SOC]);
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wl1271_write32(wl, 0x00A02360, 0xD0078);
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wl1271_write32(wl, 0x00A0236c, 0x12);
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wl1271_write32(wl, 0x00A02390, 0x20118);
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}
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static void wl18xx_boot_soft_reset(struct wl1271 *wl)
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{
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/* disable Rx/Tx */
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wl1271_write32(wl, WL18XX_ENABLE, 0x0);
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/* disable auto calibration on start*/
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wl1271_write32(wl, WL18XX_SPARE_A2, 0xffff);
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}
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static int wl18xx_pre_boot(struct wl1271 *wl)
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{
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/* TODO: add hw_pg_ver reading */
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wl18xx_set_clk(wl);
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/* Continue the ELP wake up sequence */
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wl1271_write32(wl, WL18XX_WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
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udelay(500);
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wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
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/* Disable interrupts */
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wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
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wl18xx_boot_soft_reset(wl);
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return 0;
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}
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static void wl18xx_pre_upload(struct wl1271 *wl)
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{
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u32 tmp;
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wlcore_set_partition(wl, &wl->ptable[PART_BOOT]);
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/* TODO: check if this is all needed */
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wl1271_write32(wl, WL18XX_EEPROMLESS_IND, WL18XX_EEPROMLESS_IND);
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tmp = wlcore_read_reg(wl, REG_CHIP_ID_B);
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wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
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tmp = wl1271_read32(wl, WL18XX_SCR_PAD2);
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}
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static void wl18xx_set_mac_and_phy(struct wl1271 *wl)
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{
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struct wl18xx_mac_and_phy_params params;
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memset(¶ms, 0, sizeof(params));
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params.phy_standalone = wl18xx_default_conf.phy.phy_standalone;
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params.rdl = wl18xx_default_conf.phy.rdl;
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params.enable_clpc = wl18xx_default_conf.phy.enable_clpc;
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params.enable_tx_low_pwr_on_siso_rdl =
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wl18xx_default_conf.phy.enable_tx_low_pwr_on_siso_rdl;
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params.auto_detect = wl18xx_default_conf.phy.auto_detect;
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params.dedicated_fem = wl18xx_default_conf.phy.dedicated_fem;
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params.low_band_component = wl18xx_default_conf.phy.low_band_component;
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params.low_band_component_type =
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wl18xx_default_conf.phy.low_band_component_type;
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params.high_band_component =
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wl18xx_default_conf.phy.high_band_component;
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params.high_band_component_type =
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wl18xx_default_conf.phy.high_band_component_type;
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params.number_of_assembled_ant2_4 =
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wl18xx_default_conf.phy.number_of_assembled_ant2_4;
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params.number_of_assembled_ant5 =
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wl18xx_default_conf.phy.number_of_assembled_ant5;
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params.external_pa_dc2dc = wl18xx_default_conf.phy.external_pa_dc2dc;
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params.tcxo_ldo_voltage = wl18xx_default_conf.phy.tcxo_ldo_voltage;
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params.xtal_itrim_val = wl18xx_default_conf.phy.xtal_itrim_val;
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params.srf_state = wl18xx_default_conf.phy.srf_state;
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params.io_configuration = wl18xx_default_conf.phy.io_configuration;
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params.sdio_configuration = wl18xx_default_conf.phy.sdio_configuration;
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params.settings = wl18xx_default_conf.phy.settings;
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params.rx_profile = wl18xx_default_conf.phy.rx_profile;
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params.primary_clock_setting_time =
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wl18xx_default_conf.phy.primary_clock_setting_time;
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params.clock_valid_on_wake_up =
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wl18xx_default_conf.phy.clock_valid_on_wake_up;
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params.secondary_clock_setting_time =
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wl18xx_default_conf.phy.secondary_clock_setting_time;
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/* TODO: hardcoded for now */
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params.board_type = BOARD_TYPE_DVP_EVB_18XX;
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wlcore_set_partition(wl, &wl->ptable[PART_PHY_INIT]);
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wl1271_write(wl, WL18XX_PHY_INIT_MEM_ADDR, (u8 *)¶ms,
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sizeof(params), false);
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}
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static void wl18xx_enable_interrupts(struct wl1271 *wl)
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{
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wlcore_write_reg(wl, REG_INTERRUPT_MASK, WL1271_ACX_ALL_EVENTS_VECTOR);
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wlcore_enable_interrupts(wl);
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wlcore_write_reg(wl, REG_INTERRUPT_MASK,
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WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
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}
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static int wl18xx_boot(struct wl1271 *wl)
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{
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int ret;
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ret = wl18xx_pre_boot(wl);
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if (ret < 0)
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goto out;
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ret = wlcore_boot_upload_nvs(wl);
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if (ret < 0)
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goto out;
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wl18xx_pre_upload(wl);
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ret = wlcore_boot_upload_firmware(wl);
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if (ret < 0)
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goto out;
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|
|
wl18xx_set_mac_and_phy(wl);
|
|
|
|
ret = wlcore_boot_run_firmware(wl);
|
|
if (ret < 0)
|
|
goto out;
|
|
|
|
wl18xx_enable_interrupts(wl);
|
|
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
static void wl18xx_trigger_cmd(struct wl1271 *wl, int cmd_box_addr,
|
|
void *buf, size_t len)
|
|
{
|
|
struct wl18xx_priv *priv = wl->priv;
|
|
|
|
memcpy(priv->cmd_buf, buf, len);
|
|
memset(priv->cmd_buf + len, 0, WL18XX_CMD_MAX_SIZE - len);
|
|
|
|
wl1271_write(wl, cmd_box_addr, priv->cmd_buf, WL18XX_CMD_MAX_SIZE,
|
|
false);
|
|
}
|
|
|
|
static void wl18xx_ack_event(struct wl1271 *wl)
|
|
{
|
|
wlcore_write_reg(wl, REG_INTERRUPT_TRIG, WL18XX_INTR_TRIG_EVENT_ACK);
|
|
}
|
|
|
|
static u32 wl18xx_calc_tx_blocks(struct wl1271 *wl, u32 len, u32 spare_blks)
|
|
{
|
|
u32 blk_size = WL18XX_TX_HW_BLOCK_SIZE;
|
|
return (len + blk_size - 1) / blk_size + spare_blks;
|
|
}
|
|
|
|
static void
|
|
wl18xx_set_tx_desc_blocks(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
|
|
u32 blks, u32 spare_blks)
|
|
{
|
|
desc->wl18xx_mem.total_mem_blocks = blks;
|
|
desc->wl18xx_mem.reserved = 0;
|
|
}
|
|
|
|
static void
|
|
wl18xx_set_tx_desc_data_len(struct wl1271 *wl, struct wl1271_tx_hw_descr *desc,
|
|
struct sk_buff *skb)
|
|
{
|
|
desc->length = cpu_to_le16(skb->len);
|
|
|
|
wl1271_debug(DEBUG_TX, "tx_fill_hdr: hlid: %d "
|
|
"len: %d life: %d mem: %d", desc->hlid,
|
|
le16_to_cpu(desc->length),
|
|
le16_to_cpu(desc->life_time),
|
|
desc->wl18xx_mem.total_mem_blocks);
|
|
}
|
|
|
|
static enum wl_rx_buf_align
|
|
wl18xx_get_rx_buf_align(struct wl1271 *wl, u32 rx_desc)
|
|
{
|
|
if (rx_desc & RX_BUF_PADDED_PAYLOAD)
|
|
return WLCORE_RX_BUF_PADDED;
|
|
|
|
return WLCORE_RX_BUF_ALIGNED;
|
|
}
|
|
|
|
static u32 wl18xx_get_rx_packet_len(struct wl1271 *wl, void *rx_data,
|
|
u32 data_len)
|
|
{
|
|
struct wl1271_rx_descriptor *desc = rx_data;
|
|
|
|
/* invalid packet */
|
|
if (data_len < sizeof(*desc))
|
|
return 0;
|
|
|
|
return data_len - sizeof(*desc);
|
|
}
|
|
|
|
static void wl18xx_tx_immediate_completion(struct wl1271 *wl)
|
|
{
|
|
wl18xx_tx_immediate_complete(wl);
|
|
}
|
|
|
|
static int wl18xx_hw_init(struct wl1271 *wl)
|
|
{
|
|
int ret;
|
|
u32 host_cfg_bitmap = HOST_IF_CFG_RX_FIFO_ENABLE |
|
|
HOST_IF_CFG_ADD_RX_ALIGNMENT;
|
|
|
|
u32 sdio_align_size = 0;
|
|
|
|
/* Enable Tx SDIO padding */
|
|
if (wl->quirks & WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN) {
|
|
host_cfg_bitmap |= HOST_IF_CFG_TX_PAD_TO_SDIO_BLK;
|
|
sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
|
|
}
|
|
|
|
/* Enable Rx SDIO padding */
|
|
if (wl->quirks & WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN) {
|
|
host_cfg_bitmap |= HOST_IF_CFG_RX_PAD_TO_SDIO_BLK;
|
|
sdio_align_size = WL12XX_BUS_BLOCK_SIZE;
|
|
}
|
|
|
|
ret = wl18xx_acx_host_if_cfg_bitmap(wl, host_cfg_bitmap,
|
|
sdio_align_size,
|
|
WL18XX_TX_HW_BLOCK_SPARE,
|
|
WL18XX_HOST_IF_LEN_SIZE_FIELD);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct wlcore_ops wl18xx_ops = {
|
|
.identify_chip = wl18xx_identify_chip,
|
|
.boot = wl18xx_boot,
|
|
.trigger_cmd = wl18xx_trigger_cmd,
|
|
.ack_event = wl18xx_ack_event,
|
|
.calc_tx_blocks = wl18xx_calc_tx_blocks,
|
|
.set_tx_desc_blocks = wl18xx_set_tx_desc_blocks,
|
|
.set_tx_desc_data_len = wl18xx_set_tx_desc_data_len,
|
|
.get_rx_buf_align = wl18xx_get_rx_buf_align,
|
|
.get_rx_packet_len = wl18xx_get_rx_packet_len,
|
|
.tx_immediate_compl = wl18xx_tx_immediate_completion,
|
|
.tx_delayed_compl = NULL,
|
|
.hw_init = wl18xx_hw_init,
|
|
};
|
|
|
|
int __devinit wl18xx_probe(struct platform_device *pdev)
|
|
{
|
|
struct wl1271 *wl;
|
|
struct ieee80211_hw *hw;
|
|
struct wl18xx_priv *priv;
|
|
|
|
hw = wlcore_alloc_hw(sizeof(*priv));
|
|
if (IS_ERR(hw)) {
|
|
wl1271_error("can't allocate hw");
|
|
return PTR_ERR(hw);
|
|
}
|
|
|
|
wl = hw->priv;
|
|
wl->ops = &wl18xx_ops;
|
|
wl->ptable = wl18xx_ptable;
|
|
wl->rtable = wl18xx_rtable;
|
|
wl->num_tx_desc = 32;
|
|
wl->normal_tx_spare = WL18XX_TX_HW_BLOCK_SPARE;
|
|
wl->gem_tx_spare = WL18XX_TX_HW_GEM_BLOCK_SPARE;
|
|
wl->band_rate_to_idx = wl18xx_band_rate_to_idx;
|
|
wl->hw_tx_rate_tbl_size = WL18XX_CONF_HW_RXTX_RATE_MAX;
|
|
wl->hw_min_ht_rate = WL18XX_CONF_HW_RXTX_RATE_MCS0;
|
|
wl->fw_status_priv_len = sizeof(struct wl18xx_fw_status_priv);
|
|
return wlcore_probe(wl, pdev);
|
|
}
|
|
|
|
static const struct platform_device_id wl18xx_id_table[] __devinitconst = {
|
|
{ "wl18xx", 0 },
|
|
{ } /* Terminating Entry */
|
|
};
|
|
MODULE_DEVICE_TABLE(platform, wl18xx_id_table);
|
|
|
|
static struct platform_driver wl18xx_driver = {
|
|
.probe = wl18xx_probe,
|
|
.remove = __devexit_p(wlcore_remove),
|
|
.id_table = wl18xx_id_table,
|
|
.driver = {
|
|
.name = "wl18xx_driver",
|
|
.owner = THIS_MODULE,
|
|
}
|
|
};
|
|
|
|
static int __init wl18xx_init(void)
|
|
{
|
|
return platform_driver_register(&wl18xx_driver);
|
|
}
|
|
module_init(wl18xx_init);
|
|
|
|
static void __exit wl18xx_exit(void)
|
|
{
|
|
platform_driver_unregister(&wl18xx_driver);
|
|
}
|
|
module_exit(wl18xx_exit);
|
|
|
|
MODULE_LICENSE("GPL v2");
|
|
MODULE_AUTHOR("Luciano Coelho <coelho@ti.com>");
|
|
MODULE_FIRMWARE(WL18XX_FW_NAME);
|