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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-25 10:49:25 +07:00
c566538552
Choose console BPP that supports RGB and remove the old fbdev bpp selection code. LCDC on AM335x has red and blue wires switched between 24 bit and 16 bit colors. If 24 format is wired for RGB colors, the 16 bit format is wired for BGR. drm_fbdev_cma_init() does not currently like anything else but RGB formats, so we must choose such bytes per pixel value that supports RGB. Signed-off-by: Jyri Sarha <jsarha@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
768 lines
19 KiB
C
768 lines
19 KiB
C
/*
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* Copyright (C) 2012 Texas Instruments
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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/* LCDC DRM driver, based on da8xx-fb */
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#include <linux/component.h>
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#include <linux/pinctrl/consumer.h>
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#include <linux/suspend.h>
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#include <drm/drm_atomic.h>
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#include <drm/drm_atomic_helper.h>
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#include "tilcdc_drv.h"
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#include "tilcdc_regs.h"
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#include "tilcdc_tfp410.h"
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#include "tilcdc_panel.h"
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#include "tilcdc_external.h"
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#include "drm_fb_helper.h"
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static LIST_HEAD(module_list);
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static const u32 tilcdc_rev1_formats[] = { DRM_FORMAT_RGB565 };
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static const u32 tilcdc_straight_formats[] = { DRM_FORMAT_RGB565,
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DRM_FORMAT_BGR888,
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DRM_FORMAT_XBGR8888 };
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static const u32 tilcdc_crossed_formats[] = { DRM_FORMAT_BGR565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_XRGB8888 };
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static const u32 tilcdc_legacy_formats[] = { DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_XRGB8888 };
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void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
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const struct tilcdc_module_ops *funcs)
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{
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mod->name = name;
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mod->funcs = funcs;
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INIT_LIST_HEAD(&mod->list);
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list_add(&mod->list, &module_list);
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}
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void tilcdc_module_cleanup(struct tilcdc_module *mod)
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{
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list_del(&mod->list);
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}
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static struct of_device_id tilcdc_of_match[];
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static struct drm_framebuffer *tilcdc_fb_create(struct drm_device *dev,
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struct drm_file *file_priv, const struct drm_mode_fb_cmd2 *mode_cmd)
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{
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return drm_fb_cma_create(dev, file_priv, mode_cmd);
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}
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static void tilcdc_fb_output_poll_changed(struct drm_device *dev)
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{
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struct tilcdc_drm_private *priv = dev->dev_private;
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drm_fbdev_cma_hotplug_event(priv->fbdev);
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}
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int tilcdc_atomic_check(struct drm_device *dev,
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struct drm_atomic_state *state)
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{
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int ret;
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ret = drm_atomic_helper_check_modeset(dev, state);
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if (ret)
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return ret;
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ret = drm_atomic_helper_check_planes(dev, state);
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if (ret)
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return ret;
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/*
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* tilcdc ->atomic_check can update ->mode_changed if pixel format
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* changes, hence will we check modeset changes again.
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*/
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ret = drm_atomic_helper_check_modeset(dev, state);
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if (ret)
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return ret;
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return ret;
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}
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static int tilcdc_commit(struct drm_device *dev,
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struct drm_atomic_state *state,
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bool async)
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{
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int ret;
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ret = drm_atomic_helper_prepare_planes(dev, state);
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if (ret)
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return ret;
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drm_atomic_helper_swap_state(state, true);
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/*
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* Everything below can be run asynchronously without the need to grab
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* any modeset locks at all under one condition: It must be guaranteed
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* that the asynchronous work has either been cancelled (if the driver
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* supports it, which at least requires that the framebuffers get
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* cleaned up with drm_atomic_helper_cleanup_planes()) or completed
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* before the new state gets committed on the software side with
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* drm_atomic_helper_swap_state().
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*
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* This scheme allows new atomic state updates to be prepared and
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* checked in parallel to the asynchronous completion of the previous
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* update. Which is important since compositors need to figure out the
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* composition of the next frame right after having submitted the
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* current layout.
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*/
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/* Keep HW on while we commit the state. */
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pm_runtime_get_sync(dev->dev);
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drm_atomic_helper_commit_modeset_disables(dev, state);
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drm_atomic_helper_commit_planes(dev, state, 0);
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drm_atomic_helper_commit_modeset_enables(dev, state);
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/* Now HW should remain on if need becase the crtc is enabled */
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pm_runtime_put_sync(dev->dev);
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drm_atomic_helper_wait_for_vblanks(dev, state);
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drm_atomic_helper_cleanup_planes(dev, state);
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drm_atomic_state_free(state);
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return 0;
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}
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static const struct drm_mode_config_funcs mode_config_funcs = {
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.fb_create = tilcdc_fb_create,
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.output_poll_changed = tilcdc_fb_output_poll_changed,
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.atomic_check = tilcdc_atomic_check,
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.atomic_commit = tilcdc_commit,
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};
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static int modeset_init(struct drm_device *dev)
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{
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struct tilcdc_drm_private *priv = dev->dev_private;
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struct tilcdc_module *mod;
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drm_mode_config_init(dev);
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priv->crtc = tilcdc_crtc_create(dev);
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list_for_each_entry(mod, &module_list, list) {
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DBG("loading module: %s", mod->name);
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mod->funcs->modeset_init(mod, dev);
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}
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dev->mode_config.min_width = 0;
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dev->mode_config.min_height = 0;
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dev->mode_config.max_width = tilcdc_crtc_max_width(priv->crtc);
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dev->mode_config.max_height = 2048;
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dev->mode_config.funcs = &mode_config_funcs;
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return 0;
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}
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#ifdef CONFIG_CPU_FREQ
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static int cpufreq_transition(struct notifier_block *nb,
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unsigned long val, void *data)
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{
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struct tilcdc_drm_private *priv = container_of(nb,
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struct tilcdc_drm_private, freq_transition);
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if (val == CPUFREQ_POSTCHANGE) {
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if (priv->lcd_fck_rate != clk_get_rate(priv->clk)) {
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priv->lcd_fck_rate = clk_get_rate(priv->clk);
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tilcdc_crtc_update_clk(priv->crtc);
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}
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}
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return 0;
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}
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#endif
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/*
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* DRM operations:
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*/
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static int tilcdc_unload(struct drm_device *dev)
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{
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struct tilcdc_drm_private *priv = dev->dev_private;
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tilcdc_crtc_disable(priv->crtc);
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tilcdc_remove_external_encoders(dev);
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drm_fbdev_cma_fini(priv->fbdev);
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drm_kms_helper_poll_fini(dev);
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drm_mode_config_cleanup(dev);
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drm_vblank_cleanup(dev);
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drm_irq_uninstall(dev);
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#ifdef CONFIG_CPU_FREQ
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cpufreq_unregister_notifier(&priv->freq_transition,
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CPUFREQ_TRANSITION_NOTIFIER);
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#endif
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if (priv->clk)
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clk_put(priv->clk);
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if (priv->mmio)
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iounmap(priv->mmio);
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flush_workqueue(priv->wq);
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destroy_workqueue(priv->wq);
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dev->dev_private = NULL;
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pm_runtime_disable(dev->dev);
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return 0;
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}
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static int tilcdc_load(struct drm_device *dev, unsigned long flags)
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{
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struct platform_device *pdev = dev->platformdev;
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struct device_node *node = pdev->dev.of_node;
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struct tilcdc_drm_private *priv;
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struct resource *res;
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u32 bpp = 0;
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int ret;
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priv = devm_kzalloc(dev->dev, sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(dev->dev, "failed to allocate private data\n");
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return -ENOMEM;
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}
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dev->dev_private = priv;
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priv->is_componentized =
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tilcdc_get_external_components(dev->dev, NULL) > 0;
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priv->wq = alloc_ordered_workqueue("tilcdc", 0);
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if (!priv->wq) {
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ret = -ENOMEM;
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goto fail_unset_priv;
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}
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(dev->dev, "failed to get memory resource\n");
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ret = -EINVAL;
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goto fail_free_wq;
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}
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priv->mmio = ioremap_nocache(res->start, resource_size(res));
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if (!priv->mmio) {
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dev_err(dev->dev, "failed to ioremap\n");
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ret = -ENOMEM;
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goto fail_free_wq;
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}
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priv->clk = clk_get(dev->dev, "fck");
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if (IS_ERR(priv->clk)) {
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dev_err(dev->dev, "failed to get functional clock\n");
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ret = -ENODEV;
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goto fail_iounmap;
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}
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#ifdef CONFIG_CPU_FREQ
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priv->lcd_fck_rate = clk_get_rate(priv->clk);
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priv->freq_transition.notifier_call = cpufreq_transition;
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ret = cpufreq_register_notifier(&priv->freq_transition,
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CPUFREQ_TRANSITION_NOTIFIER);
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if (ret) {
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dev_err(dev->dev, "failed to register cpufreq notifier\n");
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goto fail_put_clk;
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}
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#endif
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if (of_property_read_u32(node, "max-bandwidth", &priv->max_bandwidth))
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priv->max_bandwidth = TILCDC_DEFAULT_MAX_BANDWIDTH;
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DBG("Maximum Bandwidth Value %d", priv->max_bandwidth);
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if (of_property_read_u32(node, "ti,max-width", &priv->max_width))
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priv->max_width = TILCDC_DEFAULT_MAX_WIDTH;
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DBG("Maximum Horizontal Pixel Width Value %dpixels", priv->max_width);
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if (of_property_read_u32(node, "ti,max-pixelclock",
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&priv->max_pixelclock))
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priv->max_pixelclock = TILCDC_DEFAULT_MAX_PIXELCLOCK;
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DBG("Maximum Pixel Clock Value %dKHz", priv->max_pixelclock);
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pm_runtime_enable(dev->dev);
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/* Determine LCD IP Version */
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pm_runtime_get_sync(dev->dev);
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switch (tilcdc_read(dev, LCDC_PID_REG)) {
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case 0x4c100102:
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priv->rev = 1;
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break;
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case 0x4f200800:
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case 0x4f201000:
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priv->rev = 2;
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break;
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default:
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dev_warn(dev->dev, "Unknown PID Reg value 0x%08x, "
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"defaulting to LCD revision 1\n",
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tilcdc_read(dev, LCDC_PID_REG));
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priv->rev = 1;
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break;
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}
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pm_runtime_put_sync(dev->dev);
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if (priv->rev == 1) {
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DBG("Revision 1 LCDC supports only RGB565 format");
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priv->pixelformats = tilcdc_rev1_formats;
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priv->num_pixelformats = ARRAY_SIZE(tilcdc_rev1_formats);
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bpp = 16;
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} else {
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const char *str = "\0";
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of_property_read_string(node, "blue-and-red-wiring", &str);
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if (0 == strcmp(str, "crossed")) {
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DBG("Configured for crossed blue and red wires");
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priv->pixelformats = tilcdc_crossed_formats;
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priv->num_pixelformats =
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ARRAY_SIZE(tilcdc_crossed_formats);
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bpp = 32; /* Choose bpp with RGB support for fbdef */
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} else if (0 == strcmp(str, "straight")) {
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DBG("Configured for straight blue and red wires");
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priv->pixelformats = tilcdc_straight_formats;
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priv->num_pixelformats =
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ARRAY_SIZE(tilcdc_straight_formats);
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bpp = 16; /* Choose bpp with RGB support for fbdef */
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} else {
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DBG("Blue and red wiring '%s' unknown, use legacy mode",
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str);
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priv->pixelformats = tilcdc_legacy_formats;
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priv->num_pixelformats =
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ARRAY_SIZE(tilcdc_legacy_formats);
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bpp = 16; /* This is just a guess */
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}
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}
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ret = modeset_init(dev);
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if (ret < 0) {
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dev_err(dev->dev, "failed to initialize mode setting\n");
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goto fail_cpufreq_unregister;
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}
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platform_set_drvdata(pdev, dev);
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if (priv->is_componentized) {
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ret = component_bind_all(dev->dev, dev);
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if (ret < 0)
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goto fail_mode_config_cleanup;
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ret = tilcdc_add_external_encoders(dev);
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if (ret < 0)
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goto fail_component_cleanup;
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}
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if ((priv->num_encoders == 0) || (priv->num_connectors == 0)) {
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dev_err(dev->dev, "no encoders/connectors found\n");
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ret = -ENXIO;
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goto fail_external_cleanup;
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}
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ret = drm_vblank_init(dev, 1);
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if (ret < 0) {
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dev_err(dev->dev, "failed to initialize vblank\n");
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goto fail_external_cleanup;
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}
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ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
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if (ret < 0) {
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dev_err(dev->dev, "failed to install IRQ handler\n");
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goto fail_vblank_cleanup;
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}
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drm_mode_config_reset(dev);
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priv->fbdev = drm_fbdev_cma_init(dev, bpp,
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dev->mode_config.num_crtc,
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dev->mode_config.num_connector);
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if (IS_ERR(priv->fbdev)) {
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ret = PTR_ERR(priv->fbdev);
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goto fail_irq_uninstall;
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}
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drm_kms_helper_poll_init(dev);
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return 0;
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fail_irq_uninstall:
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drm_irq_uninstall(dev);
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fail_vblank_cleanup:
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drm_vblank_cleanup(dev);
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fail_mode_config_cleanup:
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drm_mode_config_cleanup(dev);
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fail_component_cleanup:
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if (priv->is_componentized)
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component_unbind_all(dev->dev, dev);
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fail_external_cleanup:
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tilcdc_remove_external_encoders(dev);
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fail_cpufreq_unregister:
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pm_runtime_disable(dev->dev);
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#ifdef CONFIG_CPU_FREQ
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cpufreq_unregister_notifier(&priv->freq_transition,
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CPUFREQ_TRANSITION_NOTIFIER);
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fail_put_clk:
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#endif
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clk_put(priv->clk);
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fail_iounmap:
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iounmap(priv->mmio);
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fail_free_wq:
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flush_workqueue(priv->wq);
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destroy_workqueue(priv->wq);
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fail_unset_priv:
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dev->dev_private = NULL;
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return ret;
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}
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static void tilcdc_lastclose(struct drm_device *dev)
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{
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struct tilcdc_drm_private *priv = dev->dev_private;
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drm_fbdev_cma_restore_mode(priv->fbdev);
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}
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static irqreturn_t tilcdc_irq(int irq, void *arg)
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{
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struct drm_device *dev = arg;
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struct tilcdc_drm_private *priv = dev->dev_private;
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return tilcdc_crtc_irq(priv->crtc);
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}
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static int tilcdc_enable_vblank(struct drm_device *dev, unsigned int pipe)
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{
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return 0;
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}
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static void tilcdc_disable_vblank(struct drm_device *dev, unsigned int pipe)
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{
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return;
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}
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#if defined(CONFIG_DEBUG_FS)
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static const struct {
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const char *name;
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uint8_t rev;
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uint8_t save;
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uint32_t reg;
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} registers[] = {
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#define REG(rev, save, reg) { #reg, rev, save, reg }
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/* exists in revision 1: */
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REG(1, false, LCDC_PID_REG),
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REG(1, true, LCDC_CTRL_REG),
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REG(1, false, LCDC_STAT_REG),
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REG(1, true, LCDC_RASTER_CTRL_REG),
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REG(1, true, LCDC_RASTER_TIMING_0_REG),
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REG(1, true, LCDC_RASTER_TIMING_1_REG),
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REG(1, true, LCDC_RASTER_TIMING_2_REG),
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REG(1, true, LCDC_DMA_CTRL_REG),
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REG(1, true, LCDC_DMA_FB_BASE_ADDR_0_REG),
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REG(1, true, LCDC_DMA_FB_CEILING_ADDR_0_REG),
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REG(1, true, LCDC_DMA_FB_BASE_ADDR_1_REG),
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REG(1, true, LCDC_DMA_FB_CEILING_ADDR_1_REG),
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/* new in revision 2: */
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REG(2, false, LCDC_RAW_STAT_REG),
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REG(2, false, LCDC_MASKED_STAT_REG),
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REG(2, true, LCDC_INT_ENABLE_SET_REG),
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REG(2, false, LCDC_INT_ENABLE_CLR_REG),
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REG(2, false, LCDC_END_OF_INT_IND_REG),
|
|
REG(2, true, LCDC_CLK_ENABLE_REG),
|
|
#undef REG
|
|
};
|
|
|
|
#endif
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
static int tilcdc_regs_show(struct seq_file *m, void *arg)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct tilcdc_drm_private *priv = dev->dev_private;
|
|
unsigned i;
|
|
|
|
pm_runtime_get_sync(dev->dev);
|
|
|
|
seq_printf(m, "revision: %d\n", priv->rev);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(registers); i++)
|
|
if (priv->rev >= registers[i].rev)
|
|
seq_printf(m, "%s:\t %08x\n", registers[i].name,
|
|
tilcdc_read(dev, registers[i].reg));
|
|
|
|
pm_runtime_put_sync(dev->dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tilcdc_mm_show(struct seq_file *m, void *arg)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
|
|
}
|
|
|
|
static struct drm_info_list tilcdc_debugfs_list[] = {
|
|
{ "regs", tilcdc_regs_show, 0 },
|
|
{ "mm", tilcdc_mm_show, 0 },
|
|
{ "fb", drm_fb_cma_debugfs_show, 0 },
|
|
};
|
|
|
|
static int tilcdc_debugfs_init(struct drm_minor *minor)
|
|
{
|
|
struct drm_device *dev = minor->dev;
|
|
struct tilcdc_module *mod;
|
|
int ret;
|
|
|
|
ret = drm_debugfs_create_files(tilcdc_debugfs_list,
|
|
ARRAY_SIZE(tilcdc_debugfs_list),
|
|
minor->debugfs_root, minor);
|
|
|
|
list_for_each_entry(mod, &module_list, list)
|
|
if (mod->funcs->debugfs_init)
|
|
mod->funcs->debugfs_init(mod, minor);
|
|
|
|
if (ret) {
|
|
dev_err(dev->dev, "could not install tilcdc_debugfs_list\n");
|
|
return ret;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void tilcdc_debugfs_cleanup(struct drm_minor *minor)
|
|
{
|
|
struct tilcdc_module *mod;
|
|
drm_debugfs_remove_files(tilcdc_debugfs_list,
|
|
ARRAY_SIZE(tilcdc_debugfs_list), minor);
|
|
|
|
list_for_each_entry(mod, &module_list, list)
|
|
if (mod->funcs->debugfs_cleanup)
|
|
mod->funcs->debugfs_cleanup(mod, minor);
|
|
}
|
|
#endif
|
|
|
|
static const struct file_operations fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.unlocked_ioctl = drm_ioctl,
|
|
#ifdef CONFIG_COMPAT
|
|
.compat_ioctl = drm_compat_ioctl,
|
|
#endif
|
|
.poll = drm_poll,
|
|
.read = drm_read,
|
|
.llseek = no_llseek,
|
|
.mmap = drm_gem_cma_mmap,
|
|
};
|
|
|
|
static struct drm_driver tilcdc_driver = {
|
|
.driver_features = (DRIVER_HAVE_IRQ | DRIVER_GEM | DRIVER_MODESET |
|
|
DRIVER_PRIME | DRIVER_ATOMIC),
|
|
.load = tilcdc_load,
|
|
.unload = tilcdc_unload,
|
|
.lastclose = tilcdc_lastclose,
|
|
.irq_handler = tilcdc_irq,
|
|
.get_vblank_counter = drm_vblank_no_hw_counter,
|
|
.enable_vblank = tilcdc_enable_vblank,
|
|
.disable_vblank = tilcdc_disable_vblank,
|
|
.gem_free_object_unlocked = drm_gem_cma_free_object,
|
|
.gem_vm_ops = &drm_gem_cma_vm_ops,
|
|
.dumb_create = drm_gem_cma_dumb_create,
|
|
.dumb_map_offset = drm_gem_cma_dumb_map_offset,
|
|
.dumb_destroy = drm_gem_dumb_destroy,
|
|
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
.gem_prime_import = drm_gem_prime_import,
|
|
.gem_prime_export = drm_gem_prime_export,
|
|
.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
|
|
.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
|
|
.gem_prime_vmap = drm_gem_cma_prime_vmap,
|
|
.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
|
|
.gem_prime_mmap = drm_gem_cma_prime_mmap,
|
|
#ifdef CONFIG_DEBUG_FS
|
|
.debugfs_init = tilcdc_debugfs_init,
|
|
.debugfs_cleanup = tilcdc_debugfs_cleanup,
|
|
#endif
|
|
.fops = &fops,
|
|
.name = "tilcdc",
|
|
.desc = "TI LCD Controller DRM",
|
|
.date = "20121205",
|
|
.major = 1,
|
|
.minor = 0,
|
|
};
|
|
|
|
/*
|
|
* Power management:
|
|
*/
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int tilcdc_pm_suspend(struct device *dev)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
struct tilcdc_drm_private *priv = ddev->dev_private;
|
|
|
|
priv->saved_state = drm_atomic_helper_suspend(ddev);
|
|
|
|
/* Select sleep pin state */
|
|
pinctrl_pm_select_sleep_state(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int tilcdc_pm_resume(struct device *dev)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
struct tilcdc_drm_private *priv = ddev->dev_private;
|
|
int ret = 0;
|
|
|
|
/* Select default pin state */
|
|
pinctrl_pm_select_default_state(dev);
|
|
|
|
if (priv->saved_state)
|
|
ret = drm_atomic_helper_resume(ddev, priv->saved_state);
|
|
|
|
return ret;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops tilcdc_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(tilcdc_pm_suspend, tilcdc_pm_resume)
|
|
};
|
|
|
|
/*
|
|
* Platform driver:
|
|
*/
|
|
|
|
static int tilcdc_bind(struct device *dev)
|
|
{
|
|
return drm_platform_init(&tilcdc_driver, to_platform_device(dev));
|
|
}
|
|
|
|
static void tilcdc_unbind(struct device *dev)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
|
|
/* Check if a subcomponent has already triggered the unloading. */
|
|
if (!ddev->dev_private)
|
|
return;
|
|
|
|
drm_put_dev(dev_get_drvdata(dev));
|
|
}
|
|
|
|
static const struct component_master_ops tilcdc_comp_ops = {
|
|
.bind = tilcdc_bind,
|
|
.unbind = tilcdc_unbind,
|
|
};
|
|
|
|
static int tilcdc_pdev_probe(struct platform_device *pdev)
|
|
{
|
|
struct component_match *match = NULL;
|
|
int ret;
|
|
|
|
/* bail out early if no DT data: */
|
|
if (!pdev->dev.of_node) {
|
|
dev_err(&pdev->dev, "device-tree data is missing\n");
|
|
return -ENXIO;
|
|
}
|
|
|
|
ret = tilcdc_get_external_components(&pdev->dev, &match);
|
|
if (ret < 0)
|
|
return ret;
|
|
else if (ret == 0)
|
|
return drm_platform_init(&tilcdc_driver, pdev);
|
|
else
|
|
return component_master_add_with_match(&pdev->dev,
|
|
&tilcdc_comp_ops,
|
|
match);
|
|
}
|
|
|
|
static int tilcdc_pdev_remove(struct platform_device *pdev)
|
|
{
|
|
int ret;
|
|
|
|
ret = tilcdc_get_external_components(&pdev->dev, NULL);
|
|
if (ret < 0)
|
|
return ret;
|
|
else if (ret == 0)
|
|
drm_put_dev(platform_get_drvdata(pdev));
|
|
else
|
|
component_master_del(&pdev->dev, &tilcdc_comp_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct of_device_id tilcdc_of_match[] = {
|
|
{ .compatible = "ti,am33xx-tilcdc", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, tilcdc_of_match);
|
|
|
|
static struct platform_driver tilcdc_platform_driver = {
|
|
.probe = tilcdc_pdev_probe,
|
|
.remove = tilcdc_pdev_remove,
|
|
.driver = {
|
|
.name = "tilcdc",
|
|
.pm = &tilcdc_pm_ops,
|
|
.of_match_table = tilcdc_of_match,
|
|
},
|
|
};
|
|
|
|
static int __init tilcdc_drm_init(void)
|
|
{
|
|
DBG("init");
|
|
tilcdc_tfp410_init();
|
|
tilcdc_panel_init();
|
|
return platform_driver_register(&tilcdc_platform_driver);
|
|
}
|
|
|
|
static void __exit tilcdc_drm_fini(void)
|
|
{
|
|
DBG("fini");
|
|
platform_driver_unregister(&tilcdc_platform_driver);
|
|
tilcdc_panel_fini();
|
|
tilcdc_tfp410_fini();
|
|
}
|
|
|
|
module_init(tilcdc_drm_init);
|
|
module_exit(tilcdc_drm_fini);
|
|
|
|
MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
|
|
MODULE_DESCRIPTION("TI LCD Controller DRM Driver");
|
|
MODULE_LICENSE("GPL");
|