Felix Kuehling b80cd524ac drm/amdgpu: Improve Vega20 XGMI TLB flush workaround ... Using a heavy-weight TLB flush once is not sufficient. Concurrent memory accesses in the same TLB cache line can re-populate TLB entries from stale texture cache (TC) entries while the heavy-weight TLB flush is in progress. To fix this race condition, perform another TLB flush after the heavy-weight one, when TC is known to be clean. Move the workaround into the low-level TLB flushing functions. This way they apply to amdgpu as well, and KIQ-based TLB flush only needs to synchronize once. Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Reviewed-by: shaoyun liu <shaoyun.liu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-02-25 11:01:57 -05:00
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acp	drm/amdgpu: fix license on Kconfig and Makefiles	2019-12-11 15:22:08 -05:00
amdgpu	drm/amdgpu: Improve Vega20 XGMI TLB flush workaround	2020-02-25 11:01:57 -05:00
amdkfd	drm/amdkfd: refactor runtime pm for baco	2020-02-12 16:00:54 -05:00
display	drm/amd/display: Don't take the address of skip_scdc_overwrite in dc_link_detect_helper	2020-02-19 10:36:26 -05:00
include	amdgpu/gmc_v9: save/restore sdpif regs during S3	2020-02-25 11:01:26 -05:00
powerplay	drm/amdgpu: fix memory leak during TDR test(v2)	2020-02-25 11:01:25 -05:00