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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 02:36:49 +07:00
ad0de58bfe
The actual frequency was updated in commit ae142bd997 ("ARM: mvebu:
Fix the main PLL frequency on Armada 375, 38x and 39x SoCs") but the
comment was not updated. Update it now.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
591 lines
16 KiB
Plaintext
591 lines
16 KiB
Plaintext
/*
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* Device Tree Include file for Marvell Armada 39x family of SoCs.
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*
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* Copyright (C) 2015 Marvell
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*
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* Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This file is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This file is distributed in the hope that it will be useful
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Or, alternatively
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "skeleton.dtsi"
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
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/ {
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model = "Marvell Armada 39x family SoC";
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compatible = "marvell,armada390";
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aliases {
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gpio0 = &gpio0;
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gpio1 = &gpio1;
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serial0 = &uart0;
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serial1 = &uart1;
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serial2 = &uart2;
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serial3 = &uart3;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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enable-method = "marvell,armada-390-smp";
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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};
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts-extended = <&mpic 3>;
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};
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soc {
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compatible = "marvell,armada390-mbus", "marvell,armadaxp-mbus",
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"simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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controller = <&mbusc>;
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interrupt-parent = <&gic>;
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pcie-mem-aperture = <0xe0000000 0x8000000>;
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pcie-io-aperture = <0xe8000000 0x100000>;
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bootrom {
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compatible = "marvell,bootrom";
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reg = <MBUS_ID(0x01, 0x1d) 0 0x200000>;
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};
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internal-regs {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
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L2: cache-controller@8000 {
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compatible = "arm,pl310-cache";
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reg = <0x8000 0x1000>;
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cache-unified;
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cache-level = <2>;
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arm,double-linefill-incr = <1>;
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arm,double-linefill-wrap = <0>;
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arm,double-linefill = <1>;
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prefetch-data = <1>;
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};
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scu@c000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0xc000 0x100>;
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};
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timer@c600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xc600 0x20>;
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interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
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clocks = <&coreclk 2>;
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};
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gic: interrupt-controller@d000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#size-cells = <0>;
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interrupt-controller;
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reg = <0xd000 0x1000>,
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<0xc100 0x100>;
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};
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i2c0: i2c@11000 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11000 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c1: i2c@11100 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11100 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c2: i2c@11200 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11200 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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i2c3: i2c@11300 {
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compatible = "marvell,mv64xxx-i2c";
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reg = <0x11300 0x20>;
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#address-cells = <1>;
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#size-cells = <0>;
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interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
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timeout-ms = <1000>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart0: serial@12000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12000 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart1: serial@12100 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12100 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart2: serial@12200 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12200 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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uart3: serial@12300 {
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compatible = "snps,dw-apb-uart";
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reg = <0x12300 0x100>;
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reg-shift = <2>;
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interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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reg-io-width = <1>;
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clocks = <&coreclk 0>;
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status = "disabled";
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};
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pinctrl@18000 {
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i2c0_pins: i2c0-pins {
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marvell,pins = "mpp2", "mpp3";
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marvell,function = "i2c0";
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};
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uart0_pins: uart0-pins {
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marvell,pins = "mpp0", "mpp1";
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marvell,function = "ua0";
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};
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uart1_pins: uart1-pins {
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marvell,pins = "mpp19", "mpp20";
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marvell,function = "ua1";
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};
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spi1_pins: spi1-pins {
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marvell,pins = "mpp56", "mpp57", "mpp58", "mpp59";
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marvell,function = "spi1";
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};
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nand_pins: nand-pins {
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marvell,pins = "mpp22", "mpp34", "mpp23", "mpp33",
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"mpp38", "mpp28", "mpp40", "mpp42",
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"mpp35", "mpp36", "mpp25", "mpp30",
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"mpp32";
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marvell,function = "dev";
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};
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};
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gpio0: gpio@18100 {
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compatible = "marvell,orion-gpio";
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reg = <0x18100 0x40>;
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ngpios = <32>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
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};
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gpio1: gpio@18140 {
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compatible = "marvell,orion-gpio";
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reg = <0x18140 0x40>;
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ngpios = <28>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
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};
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system-controller@18200 {
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compatible = "marvell,armada-390-system-controller",
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"marvell,armada-370-xp-system-controller";
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reg = <0x18200 0x100>;
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};
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gateclk: clock-gating-control@18220 {
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compatible = "marvell,armada-390-gating-clock";
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reg = <0x18220 0x4>;
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clocks = <&coreclk 0>;
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#clock-cells = <1>;
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};
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coreclk: mvebu-sar@18600 {
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compatible = "marvell,armada-390-core-clock";
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reg = <0x18600 0x04>;
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#clock-cells = <1>;
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};
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mbusc: mbus-controller@20000 {
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compatible = "marvell,mbus-controller";
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reg = <0x20000 0x100>, <0x20180 0x20>, <0x20250 0x8>;
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};
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mpic: interrupt-controller@20a00 {
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compatible = "marvell,mpic";
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reg = <0x20a00 0x2d0>, <0x21070 0x58>;
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#interrupt-cells = <1>;
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#size-cells = <1>;
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interrupt-controller;
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msi-controller;
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interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
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};
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timer@20300 {
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compatible = "marvell,armada-380-timer",
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"marvell,armada-xp-timer";
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reg = <0x20300 0x30>, <0x21040 0x30>;
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interrupts-extended = <&gic GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
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<&gic GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
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<&mpic 5>,
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<&mpic 6>;
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clocks = <&coreclk 2>, <&coreclk 5>;
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clock-names = "nbclk", "fixed";
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};
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watchdog@20300 {
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compatible = "marvell,armada-380-wdt";
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reg = <0x20300 0x34>, <0x20704 0x4>,
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<0x18260 0x4>;
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clocks = <&coreclk 2>, <&refclk>;
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clock-names = "nbclk", "fixed";
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};
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cpurst@20800 {
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compatible = "marvell,armada-370-cpu-reset";
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reg = <0x20800 0x10>;
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};
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mpcore-soc-ctrl@20d20 {
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compatible = "marvell,armada-380-mpcore-soc-ctrl";
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reg = <0x20d20 0x6c>;
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};
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coherency-fabric@21010 {
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compatible = "marvell,armada-380-coherency-fabric";
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reg = <0x21010 0x1c>;
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};
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pmsu@22000 {
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compatible = "marvell,armada-390-pmsu",
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"marvell,armada-380-pmsu";
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reg = <0x22000 0x1000>;
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};
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xor@60800 {
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compatible = "marvell,armada-380-xor", "marvell,orion-xor";
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reg = <0x60800 0x100
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0x60a00 0x100>;
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clocks = <&gateclk 22>;
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status = "okay";
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xor00 {
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor01 {
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interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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xor@60900 {
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compatible = "marvell,armada-380-xor", "marvell,orion-xor";
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reg = <0x60900 0x100
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0x60b00 0x100>;
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clocks = <&gateclk 28>;
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status = "okay";
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xor10 {
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
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dmacap,memcpy;
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dmacap,xor;
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};
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xor11 {
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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dmacap,memcpy;
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dmacap,xor;
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dmacap,memset;
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};
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};
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rtc@a3800 {
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compatible = "marvell,armada-380-rtc";
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reg = <0xa3800 0x20>, <0x184a0 0x0c>;
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reg-names = "rtc", "rtc-soc";
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interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
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};
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flash@d0000 {
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compatible = "marvell,armada370-nand";
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reg = <0xd0000 0x54>;
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#address-cells = <1>;
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#size-cells = <1>;
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interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&coredivclk 0>;
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status = "disabled";
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};
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sdhci@d8000 {
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compatible = "marvell,armada-380-sdhci";
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reg-names = "sdhci", "mbus", "conf-sdio3";
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reg = <0xd8000 0x1000>,
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<0xdc000 0x100>,
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<0x18454 0x4>;
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interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&gateclk 17>;
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mrvl,clk-delay-cycles = <0x1F>;
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status = "disabled";
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};
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coredivclk: clock@e4250 {
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compatible = "marvell,armada-390-corediv-clock",
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"marvell,armada-380-corediv-clock";
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reg = <0xe4250 0xc>;
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#clock-cells = <1>;
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clocks = <&mainpll>;
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clock-output-names = "nand";
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};
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thermal@e8078 {
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compatible = "marvell,armada380-thermal";
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reg = <0xe4078 0x4>, <0xe4074 0x4>;
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status = "okay";
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};
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};
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pcie-controller {
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compatible = "marvell,armada-370-pcie";
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status = "disabled";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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msi-parent = <&mpic>;
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bus-range = <0x00 0xff>;
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ranges =
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<0x82000000 0 0x80000 MBUS_ID(0xf0, 0x01) 0x80000 0 0x00002000
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0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
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0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
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0x82000000 0 0x48000 MBUS_ID(0xf0, 0x01) 0x48000 0 0x00002000
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0x82000000 0x1 0 MBUS_ID(0x08, 0xe8) 0 1 0 /* Port 0 MEM */
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0x81000000 0x1 0 MBUS_ID(0x08, 0xe0) 0 1 0 /* Port 0 IO */
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0x82000000 0x2 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 1 MEM */
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0x81000000 0x2 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 1 IO */
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0x82000000 0x3 0 MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 2 MEM */
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0x81000000 0x3 0 MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 2 IO */
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0x82000000 0x4 0 MBUS_ID(0x04, 0xb8) 0 1 0 /* Port 3 MEM */
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0x81000000 0x4 0 MBUS_ID(0x04, 0xb0) 0 1 0 /* Port 3 IO */>;
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/*
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* This port can be either x4 or x1. When
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* configured in x4 by the bootloader, then
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* pcie@4,0 is not available.
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*/
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pcie@1,0 {
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device_type = "pci";
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assigned-addresses = <0x82000800 0 0x80000 0 0x2000>;
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reg = <0x0800 0 0 0 0>;
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
|
|
0x81000000 0 0 0x81000000 0x1 0 1 0>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
marvell,pcie-port = <0>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 8>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* x1 port */
|
|
pcie@2,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
|
|
reg = <0x1000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
|
|
0x81000000 0 0 0x81000000 0x2 0 1 0>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
|
|
marvell,pcie-port = <1>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 5>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/* x1 port */
|
|
pcie@3,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
|
|
reg = <0x1800 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
|
|
0x81000000 0 0 0x81000000 0x3 0 1 0>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
|
|
marvell,pcie-port = <2>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
/*
|
|
* x1 port only available when pcie@1,0 is
|
|
* configured as a x1 port
|
|
*/
|
|
pcie@4,0 {
|
|
device_type = "pci";
|
|
assigned-addresses = <0x82000800 0 0x48000 0 0x2000>;
|
|
reg = <0x2000 0 0 0 0>;
|
|
#address-cells = <3>;
|
|
#size-cells = <2>;
|
|
#interrupt-cells = <1>;
|
|
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
|
|
0x81000000 0 0 0x81000000 0x4 0 1 0>;
|
|
interrupt-map-mask = <0 0 0 0>;
|
|
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
marvell,pcie-port = <3>;
|
|
marvell,pcie-lane = <0>;
|
|
clocks = <&gateclk 7>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
spi0: spi@10600 {
|
|
compatible = "marvell,armada-390-spi",
|
|
"marvell,orion-spi";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10600 0x50>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <0>;
|
|
interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
spi1: spi@10680 {
|
|
compatible = "marvell,armada-390-spi",
|
|
"marvell,orion-spi";
|
|
reg = <MBUS_ID(0xf0, 0x01) 0x10680 0x50>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
cell-index = <1>;
|
|
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&coreclk 0>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
/* 1 GHz fixed main PLL */
|
|
mainpll: mainpll {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <1000000000>;
|
|
};
|
|
|
|
/* 25 MHz reference crystal */
|
|
refclk: oscillator {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <25000000>;
|
|
};
|
|
};
|
|
};
|