mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 04:35:27 +07:00
b7e68d6876
This adopts a trimmed down version of the MIPS port mangling interface limited to the I/O swabbing for platforms that can't use little endian accessors. For platforms with mixed I/O spaces involving PCI it will still be necessary to enable byte swapping at the host controller level. Attention needs to be paid to all of host controller endianness, CPU endianness, and whether I/O accesses are explicitly swapped or not via SWAP_IO_SPACE. Fortunately the platforms that need this are in the minority. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
387 lines
11 KiB
C
387 lines
11 KiB
C
#ifndef __ASM_SH_IO_H
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#define __ASM_SH_IO_H
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/*
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* Convention:
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* read{b,w,l,q}/write{b,w,l,q} are for PCI,
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* while in{b,w,l}/out{b,w,l} are for ISA
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*
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* In addition we have 'pausing' versions: in{b,w,l}_p/out{b,w,l}_p
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* and 'string' versions: ins{b,w,l}/outs{b,w,l}
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*
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* While read{b,w,l,q} and write{b,w,l,q} contain memory barriers
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* automatically, there are also __raw versions, which do not.
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*/
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#include <linux/errno.h>
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#include <asm/cache.h>
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#include <asm/system.h>
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#include <asm/addrspace.h>
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#include <asm/machvec.h>
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#include <asm/pgtable.h>
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#include <asm-generic/iomap.h>
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#ifdef __KERNEL__
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#define __IO_PREFIX generic
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#include <asm/io_generic.h>
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#include <asm/io_trapped.h>
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#include <mach/mangle-port.h>
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#define __raw_writeb(v,a) (__chk_io_ptr(a), *(volatile u8 __force *)(a) = (v))
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#define __raw_writew(v,a) (__chk_io_ptr(a), *(volatile u16 __force *)(a) = (v))
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#define __raw_writel(v,a) (__chk_io_ptr(a), *(volatile u32 __force *)(a) = (v))
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#define __raw_writeq(v,a) (__chk_io_ptr(a), *(volatile u64 __force *)(a) = (v))
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#define __raw_readb(a) (__chk_io_ptr(a), *(volatile u8 __force *)(a))
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#define __raw_readw(a) (__chk_io_ptr(a), *(volatile u16 __force *)(a))
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#define __raw_readl(a) (__chk_io_ptr(a), *(volatile u32 __force *)(a))
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#define __raw_readq(a) (__chk_io_ptr(a), *(volatile u64 __force *)(a))
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#define readb_relaxed(c) ({ u8 __v = ioswabb(__raw_readb(c)); __v; })
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#define readw_relaxed(c) ({ u16 __v = ioswabw(__raw_readw(c)); __v; })
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#define readl_relaxed(c) ({ u32 __v = ioswabl(__raw_readl(c)); __v; })
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#define readq_relaxed(c) ({ u64 __v = ioswabq(__raw_readq(c)); __v; })
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#define writeb_relaxed(v,c) ((void)__raw_writeb((__force u8)ioswabb(v),c))
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#define writew_relaxed(v,c) ((void)__raw_writew((__force u16)ioswabw(v),c))
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#define writel_relaxed(v,c) ((void)__raw_writel((__force u32)ioswabl(v),c))
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#define writeq_relaxed(v,c) ((void)__raw_writeq((__force u64)ioswabq(v),c))
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#define readb(a) ({ u8 r_ = readb_relaxed(a); rmb(); r_; })
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#define readw(a) ({ u16 r_ = readw_relaxed(a); rmb(); r_; })
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#define readl(a) ({ u32 r_ = readl_relaxed(a); rmb(); r_; })
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#define readq(a) ({ u64 r_ = readq_relaxed(a); rmb(); r_; })
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#define writeb(v,a) ({ wmb(); writeb_relaxed((v),(a)); })
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#define writew(v,a) ({ wmb(); writew_relaxed((v),(a)); })
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#define writel(v,a) ({ wmb(); writel_relaxed((v),(a)); })
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#define writeq(v,a) ({ wmb(); writeq_relaxed((v),(a)); })
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#define readsb(p,d,l) __raw_readsb(p,d,l)
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#define readsw(p,d,l) __raw_readsw(p,d,l)
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#define readsl(p,d,l) __raw_readsl(p,d,l)
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#define writesb(p,d,l) __raw_writesb(p,d,l)
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#define writesw(p,d,l) __raw_writesw(p,d,l)
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#define writesl(p,d,l) __raw_writesl(p,d,l)
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#define __BUILD_UNCACHED_IO(bwlq, type) \
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static inline type read##bwlq##_uncached(unsigned long addr) \
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{ \
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type ret; \
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jump_to_uncached(); \
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ret = __raw_read##bwlq(addr); \
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back_to_cached(); \
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return ret; \
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} \
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\
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static inline void write##bwlq##_uncached(type v, unsigned long addr) \
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{ \
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jump_to_uncached(); \
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__raw_write##bwlq(v, addr); \
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back_to_cached(); \
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}
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__BUILD_UNCACHED_IO(b, u8)
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__BUILD_UNCACHED_IO(w, u16)
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__BUILD_UNCACHED_IO(l, u32)
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__BUILD_UNCACHED_IO(q, u64)
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#define __BUILD_MEMORY_STRING(pfx, bwlq, type) \
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\
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static inline void \
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pfx##writes##bwlq(volatile void __iomem *mem, const void *addr, \
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unsigned int count) \
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{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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__raw_write##bwlq(*__addr, mem); \
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__addr++; \
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} \
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} \
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\
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static inline void pfx##reads##bwlq(volatile void __iomem *mem, \
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void *addr, unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = __raw_read##bwlq(mem); \
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__addr++; \
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} \
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}
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__BUILD_MEMORY_STRING(__raw_, b, u8)
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__BUILD_MEMORY_STRING(__raw_, w, u16)
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#ifdef CONFIG_SUPERH32
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void __raw_writesl(void __iomem *addr, const void *data, int longlen);
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void __raw_readsl(const void __iomem *addr, void *data, int longlen);
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#else
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__BUILD_MEMORY_STRING(__raw_, l, u32)
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#endif
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__BUILD_MEMORY_STRING(__raw_, q, u64)
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#ifdef CONFIG_HAS_IOPORT
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/*
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* Slowdown I/O port space accesses for antique hardware.
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*/
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#undef CONF_SLOWDOWN_IO
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/*
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* On SuperH I/O ports are memory mapped, so we access them using normal
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* load/store instructions. sh_io_port_base is the virtual address to
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* which all ports are being mapped.
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*/
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extern const unsigned long sh_io_port_base;
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static inline void __set_io_port_base(unsigned long pbase)
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{
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*(unsigned long *)&sh_io_port_base = pbase;
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barrier();
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}
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#ifdef CONFIG_GENERIC_IOMAP
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#define __ioport_map ioport_map
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#else
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extern void __iomem *__ioport_map(unsigned long addr, unsigned int size);
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#endif
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#ifdef CONF_SLOWDOWN_IO
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#define SLOW_DOWN_IO __raw_readw(sh_io_port_base)
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#else
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#define SLOW_DOWN_IO
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#endif
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#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow) \
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\
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static inline void pfx##out##bwlq##p(type val, unsigned long port) \
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{ \
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volatile type *__addr; \
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\
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__addr = __ioport_map(port, sizeof(type)); \
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*__addr = val; \
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slow; \
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} \
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\
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static inline type pfx##in##bwlq##p(unsigned long port) \
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{ \
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volatile type *__addr; \
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type __val; \
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\
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__addr = __ioport_map(port, sizeof(type)); \
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__val = *__addr; \
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slow; \
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\
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return __val; \
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}
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#define __BUILD_IOPORT_PFX(bus, bwlq, type) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, ,) \
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__BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
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#define BUILDIO_IOPORT(bwlq, type) \
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__BUILD_IOPORT_PFX(, bwlq, type)
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BUILDIO_IOPORT(b, u8)
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BUILDIO_IOPORT(w, u16)
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BUILDIO_IOPORT(l, u32)
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BUILDIO_IOPORT(q, u64)
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#define __BUILD_IOPORT_STRING(bwlq, type) \
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\
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static inline void outs##bwlq(unsigned long port, const void *addr, \
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unsigned int count) \
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{ \
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const volatile type *__addr = addr; \
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\
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while (count--) { \
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out##bwlq(*__addr, port); \
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__addr++; \
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} \
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} \
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\
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static inline void ins##bwlq(unsigned long port, void *addr, \
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unsigned int count) \
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{ \
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volatile type *__addr = addr; \
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\
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while (count--) { \
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*__addr = in##bwlq(port); \
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__addr++; \
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} \
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}
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__BUILD_IOPORT_STRING(b, u8)
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__BUILD_IOPORT_STRING(w, u16)
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__BUILD_IOPORT_STRING(l, u32)
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__BUILD_IOPORT_STRING(q, u64)
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#endif
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#define IO_SPACE_LIMIT 0xffffffff
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/* synco on SH-4A, otherwise a nop */
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#define mmiowb() wmb()
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/* We really want to try and get these to memcpy etc */
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void memcpy_fromio(void *, const volatile void __iomem *, unsigned long);
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void memcpy_toio(volatile void __iomem *, const void *, unsigned long);
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void memset_io(volatile void __iomem *, int, unsigned long);
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/* Quad-word real-mode I/O, don't ask.. */
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unsigned long long peek_real_address_q(unsigned long long addr);
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unsigned long long poke_real_address_q(unsigned long long addr,
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unsigned long long val);
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#if !defined(CONFIG_MMU)
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#define virt_to_phys(address) ((unsigned long)(address))
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#define phys_to_virt(address) ((void *)(address))
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#else
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#define virt_to_phys(address) (__pa(address))
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#define phys_to_virt(address) (__va(address))
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#endif
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/*
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* On 32-bit SH, we traditionally have the whole physical address space
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* mapped at all times (as MIPS does), so "ioremap()" and "iounmap()" do
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* not need to do anything but place the address in the proper segment.
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* This is true for P1 and P2 addresses, as well as some P3 ones.
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* However, most of the P3 addresses and newer cores using extended
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* addressing need to map through page tables, so the ioremap()
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* implementation becomes a bit more complicated.
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*
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* See arch/sh/mm/ioremap.c for additional notes on this.
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*
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* We cheat a bit and always return uncachable areas until we've fixed
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* the drivers to handle caching properly.
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*
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* On the SH-5 the concept of segmentation in the 1:1 PXSEG sense simply
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* doesn't exist, so everything must go through page tables.
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*/
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#ifdef CONFIG_MMU
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void __iomem *__ioremap_caller(phys_addr_t offset, unsigned long size,
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pgprot_t prot, void *caller);
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void __iounmap(void __iomem *addr);
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static inline void __iomem *
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__ioremap(phys_addr_t offset, unsigned long size, pgprot_t prot)
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{
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return __ioremap_caller(offset, size, prot, __builtin_return_address(0));
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}
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static inline void __iomem *
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__ioremap_29bit(phys_addr_t offset, unsigned long size, pgprot_t prot)
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{
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#ifdef CONFIG_29BIT
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phys_addr_t last_addr = offset + size - 1;
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/*
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* For P1 and P2 space this is trivial, as everything is already
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* mapped. Uncached access for P1 addresses are done through P2.
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* In the P3 case or for addresses outside of the 29-bit space,
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* mapping must be done by the PMB or by using page tables.
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*/
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if (likely(PXSEG(offset) < P3SEG && PXSEG(last_addr) < P3SEG)) {
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u64 flags = pgprot_val(prot);
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/*
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* Anything using the legacy PTEA space attributes needs
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* to be kicked down to page table mappings.
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*/
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if (unlikely(flags & _PAGE_PCC_MASK))
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return NULL;
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if (unlikely(flags & _PAGE_CACHABLE))
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return (void __iomem *)P1SEGADDR(offset);
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return (void __iomem *)P2SEGADDR(offset);
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}
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/* P4 above the store queues are always mapped. */
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if (unlikely(offset >= P3_ADDR_MAX))
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return (void __iomem *)P4SEGADDR(offset);
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#endif
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return NULL;
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}
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static inline void __iomem *
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__ioremap_mode(phys_addr_t offset, unsigned long size, pgprot_t prot)
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{
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void __iomem *ret;
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ret = __ioremap_trapped(offset, size);
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if (ret)
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return ret;
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ret = __ioremap_29bit(offset, size, prot);
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if (ret)
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return ret;
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return __ioremap(offset, size, prot);
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}
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#else
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#define __ioremap(offset, size, prot) ((void __iomem *)(offset))
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#define __ioremap_mode(offset, size, prot) ((void __iomem *)(offset))
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#define __iounmap(addr) do { } while (0)
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#endif /* CONFIG_MMU */
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static inline void __iomem *ioremap(phys_addr_t offset, unsigned long size)
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{
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return __ioremap_mode(offset, size, PAGE_KERNEL_NOCACHE);
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}
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static inline void __iomem *
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ioremap_cache(phys_addr_t offset, unsigned long size)
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{
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return __ioremap_mode(offset, size, PAGE_KERNEL);
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}
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#ifdef CONFIG_HAVE_IOREMAP_PROT
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static inline void __iomem *
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ioremap_prot(phys_addr_t offset, unsigned long size, unsigned long flags)
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{
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return __ioremap_mode(offset, size, __pgprot(flags));
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}
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#endif
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#ifdef CONFIG_IOREMAP_FIXED
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extern void __iomem *ioremap_fixed(phys_addr_t, unsigned long, pgprot_t);
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extern int iounmap_fixed(void __iomem *);
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extern void ioremap_fixed_init(void);
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#else
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static inline void __iomem *
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ioremap_fixed(phys_addr_t phys_addr, unsigned long size, pgprot_t prot)
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{
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BUG();
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return NULL;
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}
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static inline void ioremap_fixed_init(void) { }
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static inline int iounmap_fixed(void __iomem *addr) { return -EINVAL; }
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#endif
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#define ioremap_nocache ioremap
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#define iounmap __iounmap
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/*
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* Convert a physical pointer to a virtual kernel pointer for /dev/mem
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* access
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*/
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#define xlate_dev_mem_ptr(p) __va(p)
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/*
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* Convert a virtual cached pointer to an uncached pointer
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*/
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#define xlate_dev_kmem_ptr(p) p
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#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
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int valid_phys_addr_range(unsigned long addr, size_t size);
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int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
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#endif /* __KERNEL__ */
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#endif /* __ASM_SH_IO_H */
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