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1727339590
The CLOCKSOURCE_OF_DECLARE macro is used widely for the timers to declare the clocksource at early stage. However, this macro is also used to initialize the clockevent if any, or the clockevent only. It was originally suggested to declare another macro to initialize a clockevent, so in order to separate the two entities even they belong to the same IP. This was not accepted because of the impact on the DT where splitting a clocksource/clockevent definition does not make sense as it is a Linux concept not a hardware description. On the other side, the clocksource has not interrupt declared while the clockevent has, so it is easy from the driver to know if the description is for a clockevent or a clocksource, IOW it could be implemented at the driver level. So instead of dealing with a named clocksource macro, let's use a more generic one: TIMER_OF_DECLARE. The patch has not functional changes. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org> Acked-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
191 lines
4.6 KiB
C
191 lines
4.6 KiB
C
/*
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* Copyright (C) Maxime Coquelin 2015
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* Author: Maxime Coquelin <mcoquelin.stm32@gmail.com>
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* License terms: GNU General Public License (GPL), version 2
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*
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* Inspired by time-efm32.c from Uwe Kleine-Koenig
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*/
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#include <linux/kernel.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/irq.h>
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#include <linux/interrupt.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#define TIM_CR1 0x00
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#define TIM_DIER 0x0c
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#define TIM_SR 0x10
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#define TIM_EGR 0x14
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#define TIM_PSC 0x28
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#define TIM_ARR 0x2c
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#define TIM_CR1_CEN BIT(0)
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#define TIM_CR1_OPM BIT(3)
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#define TIM_CR1_ARPE BIT(7)
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#define TIM_DIER_UIE BIT(0)
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#define TIM_SR_UIF BIT(0)
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#define TIM_EGR_UG BIT(0)
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struct stm32_clock_event_ddata {
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struct clock_event_device evtdev;
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unsigned periodic_top;
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void __iomem *base;
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};
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static int stm32_clock_event_shutdown(struct clock_event_device *evtdev)
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{
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struct stm32_clock_event_ddata *data =
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container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
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void *base = data->base;
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writel_relaxed(0, base + TIM_CR1);
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return 0;
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}
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static int stm32_clock_event_set_periodic(struct clock_event_device *evtdev)
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{
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struct stm32_clock_event_ddata *data =
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container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
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void *base = data->base;
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writel_relaxed(data->periodic_top, base + TIM_ARR);
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writel_relaxed(TIM_CR1_ARPE | TIM_CR1_CEN, base + TIM_CR1);
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return 0;
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}
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static int stm32_clock_event_set_next_event(unsigned long evt,
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struct clock_event_device *evtdev)
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{
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struct stm32_clock_event_ddata *data =
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container_of(evtdev, struct stm32_clock_event_ddata, evtdev);
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writel_relaxed(evt, data->base + TIM_ARR);
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writel_relaxed(TIM_CR1_ARPE | TIM_CR1_OPM | TIM_CR1_CEN,
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data->base + TIM_CR1);
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return 0;
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}
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static irqreturn_t stm32_clock_event_handler(int irq, void *dev_id)
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{
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struct stm32_clock_event_ddata *data = dev_id;
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writel_relaxed(0, data->base + TIM_SR);
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data->evtdev.event_handler(&data->evtdev);
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return IRQ_HANDLED;
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}
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static struct stm32_clock_event_ddata clock_event_ddata = {
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.evtdev = {
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.name = "stm32 clockevent",
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.features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
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.set_state_shutdown = stm32_clock_event_shutdown,
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.set_state_periodic = stm32_clock_event_set_periodic,
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.set_state_oneshot = stm32_clock_event_shutdown,
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.tick_resume = stm32_clock_event_shutdown,
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.set_next_event = stm32_clock_event_set_next_event,
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.rating = 200,
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},
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};
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static int __init stm32_clockevent_init(struct device_node *np)
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{
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struct stm32_clock_event_ddata *data = &clock_event_ddata;
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struct clk *clk;
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struct reset_control *rstc;
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unsigned long rate, max_delta;
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int irq, ret, bits, prescaler = 1;
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clk = of_clk_get(np, 0);
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if (IS_ERR(clk)) {
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ret = PTR_ERR(clk);
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pr_err("failed to get clock for clockevent (%d)\n", ret);
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goto err_clk_get;
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}
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ret = clk_prepare_enable(clk);
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if (ret) {
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pr_err("failed to enable timer clock for clockevent (%d)\n",
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ret);
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goto err_clk_enable;
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}
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rate = clk_get_rate(clk);
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rstc = of_reset_control_get(np, NULL);
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if (!IS_ERR(rstc)) {
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reset_control_assert(rstc);
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reset_control_deassert(rstc);
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}
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data->base = of_iomap(np, 0);
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if (!data->base) {
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ret = -ENXIO;
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pr_err("failed to map registers for clockevent\n");
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goto err_iomap;
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}
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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ret = -EINVAL;
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pr_err("%s: failed to get irq.\n", np->full_name);
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goto err_get_irq;
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}
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/* Detect whether the timer is 16 or 32 bits */
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writel_relaxed(~0U, data->base + TIM_ARR);
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max_delta = readl_relaxed(data->base + TIM_ARR);
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if (max_delta == ~0U) {
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prescaler = 1;
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bits = 32;
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} else {
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prescaler = 1024;
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bits = 16;
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}
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writel_relaxed(0, data->base + TIM_ARR);
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writel_relaxed(prescaler - 1, data->base + TIM_PSC);
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writel_relaxed(TIM_EGR_UG, data->base + TIM_EGR);
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writel_relaxed(TIM_DIER_UIE, data->base + TIM_DIER);
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writel_relaxed(0, data->base + TIM_SR);
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data->periodic_top = DIV_ROUND_CLOSEST(rate, prescaler * HZ);
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clockevents_config_and_register(&data->evtdev,
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DIV_ROUND_CLOSEST(rate, prescaler),
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0x1, max_delta);
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ret = request_irq(irq, stm32_clock_event_handler, IRQF_TIMER,
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"stm32 clockevent", data);
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if (ret) {
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pr_err("%s: failed to request irq.\n", np->full_name);
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goto err_get_irq;
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}
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pr_info("%s: STM32 clockevent driver initialized (%d bits)\n",
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np->full_name, bits);
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return ret;
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err_get_irq:
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iounmap(data->base);
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err_iomap:
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clk_disable_unprepare(clk);
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err_clk_enable:
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clk_put(clk);
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err_clk_get:
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return ret;
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}
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TIMER_OF_DECLARE(stm32, "st,stm32-timer", stm32_clockevent_init);
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