mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 07:34:57 +07:00
28ed756f1f
This reverts commit 555b1b651a
.
Let's try this again for 3.13. It's required for proper
interaction with alsa. Was disabled previously in 3.12
to be on the safe side since it caused problems on older
asics.
340 lines
9.8 KiB
C
340 lines
9.8 KiB
C
/*
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* Copyright 2013 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include <linux/hdmi.h>
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#include <drm/drmP.h>
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#include "radeon.h"
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#include "sid.h"
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static u32 dce6_endpoint_rreg(struct radeon_device *rdev,
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u32 block_offset, u32 reg)
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{
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unsigned long flags;
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u32 r;
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spin_lock_irqsave(&rdev->end_idx_lock, flags);
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WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
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r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset);
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spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
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return r;
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}
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static void dce6_endpoint_wreg(struct radeon_device *rdev,
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u32 block_offset, u32 reg, u32 v)
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{
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unsigned long flags;
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spin_lock_irqsave(&rdev->end_idx_lock, flags);
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if (ASIC_IS_DCE8(rdev))
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WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg);
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else
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WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset,
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AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg));
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WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v);
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spin_unlock_irqrestore(&rdev->end_idx_lock, flags);
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}
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#define RREG32_ENDPOINT(block, reg) dce6_endpoint_rreg(rdev, (block), (reg))
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#define WREG32_ENDPOINT(block, reg, v) dce6_endpoint_wreg(rdev, (block), (reg), (v))
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static void dce6_afmt_get_connected_pins(struct radeon_device *rdev)
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{
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int i;
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u32 offset, tmp;
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for (i = 0; i < rdev->audio.num_pins; i++) {
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offset = rdev->audio.pin[i].offset;
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tmp = RREG32_ENDPOINT(offset,
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AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT);
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if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1)
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rdev->audio.pin[i].connected = false;
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else
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rdev->audio.pin[i].connected = true;
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}
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}
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struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev)
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{
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int i;
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dce6_afmt_get_connected_pins(rdev);
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for (i = 0; i < rdev->audio.num_pins; i++) {
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if (rdev->audio.pin[i].connected)
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return &rdev->audio.pin[i];
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}
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DRM_ERROR("No connected audio pins found!\n");
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return NULL;
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}
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void dce6_afmt_select_pin(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u32 offset = dig->afmt->offset;
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if (!dig->afmt->pin)
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return;
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WREG32(AFMT_AUDIO_SRC_CONTROL + offset,
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AFMT_AUDIO_SRC_SELECT(dig->afmt->pin->id));
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}
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void dce6_afmt_write_latency_fields(struct drm_encoder *encoder,
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struct drm_display_mode *mode)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector = NULL;
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u32 tmp = 0, offset;
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if (!dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder) {
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radeon_connector = to_radeon_connector(connector);
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break;
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}
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}
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if (!radeon_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
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if (connector->latency_present[1])
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tmp = VIDEO_LIPSYNC(connector->video_latency[1]) |
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AUDIO_LIPSYNC(connector->audio_latency[1]);
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else
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tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
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} else {
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if (connector->latency_present[0])
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tmp = VIDEO_LIPSYNC(connector->video_latency[0]) |
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AUDIO_LIPSYNC(connector->audio_latency[0]);
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else
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tmp = VIDEO_LIPSYNC(255) | AUDIO_LIPSYNC(255);
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}
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WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp);
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}
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void dce6_afmt_write_speaker_allocation(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector = NULL;
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u32 offset, tmp;
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u8 *sadb;
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int sad_count;
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if (!dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder)
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radeon_connector = to_radeon_connector(connector);
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}
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if (!radeon_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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sad_count = drm_edid_to_speaker_allocation(radeon_connector->edid, &sadb);
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if (sad_count < 0) {
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DRM_ERROR("Couldn't read Speaker Allocation Data Block: %d\n", sad_count);
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return;
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}
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/* program the speaker allocation */
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tmp = RREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER);
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tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK);
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/* set HDMI mode */
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tmp |= HDMI_CONNECTION;
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if (sad_count)
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tmp |= SPEAKER_ALLOCATION(sadb[0]);
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else
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tmp |= SPEAKER_ALLOCATION(5); /* stereo */
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WREG32_ENDPOINT(offset, AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp);
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kfree(sadb);
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}
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void dce6_afmt_write_sad_regs(struct drm_encoder *encoder)
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{
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struct radeon_device *rdev = encoder->dev->dev_private;
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
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u32 offset;
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struct drm_connector *connector;
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struct radeon_connector *radeon_connector = NULL;
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struct cea_sad *sads;
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int i, sad_count;
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static const u16 eld_reg_to_type[][2] = {
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP },
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{ AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO },
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};
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if (!dig->afmt->pin)
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return;
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offset = dig->afmt->pin->offset;
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list_for_each_entry(connector, &encoder->dev->mode_config.connector_list, head) {
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if (connector->encoder == encoder)
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radeon_connector = to_radeon_connector(connector);
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}
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if (!radeon_connector) {
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DRM_ERROR("Couldn't find encoder's connector\n");
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return;
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}
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sad_count = drm_edid_to_sad(radeon_connector->edid, &sads);
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if (sad_count < 0) {
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DRM_ERROR("Couldn't read SADs: %d\n", sad_count);
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return;
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}
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BUG_ON(!sads);
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for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) {
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u32 value = 0;
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u8 stereo_freqs = 0;
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int max_channels = -1;
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int j;
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for (j = 0; j < sad_count; j++) {
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struct cea_sad *sad = &sads[j];
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if (sad->format == eld_reg_to_type[i][1]) {
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if (sad->channels > max_channels) {
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value = MAX_CHANNELS(sad->channels) |
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DESCRIPTOR_BYTE_2(sad->byte2) |
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SUPPORTED_FREQUENCIES(sad->freq);
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max_channels = sad->channels;
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}
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if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM)
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stereo_freqs |= sad->freq;
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else
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break;
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}
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}
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value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs);
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WREG32_ENDPOINT(offset, eld_reg_to_type[i][0], value);
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}
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kfree(sads);
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}
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static int dce6_audio_chipset_supported(struct radeon_device *rdev)
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{
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return !ASIC_IS_NODCE(rdev);
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}
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static void dce6_audio_enable(struct radeon_device *rdev,
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struct r600_audio_pin *pin,
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bool enable)
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{
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WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOTPLUG_CONTROL,
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AUDIO_ENABLED);
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DRM_INFO("%s audio %d support\n", enable ? "Enabling" : "Disabling", pin->id);
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}
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static const u32 pin_offsets[7] =
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{
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(0x5e00 - 0x5e00),
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(0x5e18 - 0x5e00),
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(0x5e30 - 0x5e00),
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(0x5e48 - 0x5e00),
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(0x5e60 - 0x5e00),
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(0x5e78 - 0x5e00),
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(0x5e90 - 0x5e00),
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};
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int dce6_audio_init(struct radeon_device *rdev)
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{
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int i;
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if (!radeon_audio || !dce6_audio_chipset_supported(rdev))
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return 0;
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rdev->audio.enabled = true;
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if (ASIC_IS_DCE8(rdev))
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rdev->audio.num_pins = 7;
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else
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rdev->audio.num_pins = 6;
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for (i = 0; i < rdev->audio.num_pins; i++) {
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rdev->audio.pin[i].channels = -1;
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rdev->audio.pin[i].rate = -1;
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rdev->audio.pin[i].bits_per_sample = -1;
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rdev->audio.pin[i].status_bits = 0;
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rdev->audio.pin[i].category_code = 0;
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rdev->audio.pin[i].connected = false;
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rdev->audio.pin[i].offset = pin_offsets[i];
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rdev->audio.pin[i].id = i;
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dce6_audio_enable(rdev, &rdev->audio.pin[i], true);
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}
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return 0;
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}
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void dce6_audio_fini(struct radeon_device *rdev)
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{
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int i;
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if (!rdev->audio.enabled)
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return;
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for (i = 0; i < rdev->audio.num_pins; i++)
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dce6_audio_enable(rdev, &rdev->audio.pin[i], false);
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rdev->audio.enabled = false;
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}
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