mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 21:16:40 +07:00
c6e970a04b
There is an include loop between netdevice.h, dsa.h, devlink.h because of NETDEV_ALIGN, making it impossible to use devlink structures in dsa.h. Break this loop by taking dsa.h out of netdevice.h, add a forward declaration of dsa_switch_tree and netdev_set_default_ethtool_ops() function, which is what netdevice.h requires. No longer having dsa.h in netdevice.h means the includes in dsa.h no longer get included. This breaks a few other files which depend on these includes. Add these directly in the affected file. Signed-off-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
615 lines
15 KiB
C
615 lines
15 KiB
C
/*
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* Broadcom Starfighter 2 DSA switch CFP support
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*
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* Copyright (C) 2016, Broadcom
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/list.h>
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#include <linux/ethtool.h>
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#include <linux/if_ether.h>
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#include <linux/in.h>
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#include <linux/netdevice.h>
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#include <net/dsa.h>
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#include <linux/bitmap.h>
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#include "bcm_sf2.h"
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#include "bcm_sf2_regs.h"
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struct cfp_udf_layout {
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u8 slices[UDF_NUM_SLICES];
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u32 mask_value;
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};
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/* UDF slices layout for a TCPv4/UDPv4 specification */
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static const struct cfp_udf_layout udf_tcpip4_layout = {
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.slices = {
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/* End of L2, byte offset 12, src IP[0:15] */
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CFG_UDF_EOL2 | 6,
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/* End of L2, byte offset 14, src IP[16:31] */
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CFG_UDF_EOL2 | 7,
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/* End of L2, byte offset 16, dst IP[0:15] */
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CFG_UDF_EOL2 | 8,
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/* End of L2, byte offset 18, dst IP[16:31] */
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CFG_UDF_EOL2 | 9,
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/* End of L3, byte offset 0, src port */
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CFG_UDF_EOL3 | 0,
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/* End of L3, byte offset 2, dst port */
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CFG_UDF_EOL3 | 1,
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0, 0, 0
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},
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.mask_value = L3_FRAMING_MASK | IPPROTO_MASK | IP_FRAG,
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};
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static inline unsigned int bcm_sf2_get_num_udf_slices(const u8 *layout)
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{
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unsigned int i, count = 0;
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for (i = 0; i < UDF_NUM_SLICES; i++) {
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if (layout[i] != 0)
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count++;
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}
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return count;
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}
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static void bcm_sf2_cfp_udf_set(struct bcm_sf2_priv *priv,
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unsigned int slice_num,
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const u8 *layout)
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{
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u32 offset = CORE_UDF_0_A_0_8_PORT_0 + slice_num * UDF_SLICE_OFFSET;
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unsigned int i;
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for (i = 0; i < UDF_NUM_SLICES; i++)
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core_writel(priv, layout[i], offset + i * 4);
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}
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static int bcm_sf2_cfp_op(struct bcm_sf2_priv *priv, unsigned int op)
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{
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unsigned int timeout = 1000;
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u32 reg;
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reg = core_readl(priv, CORE_CFP_ACC);
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reg &= ~(OP_SEL_MASK | RAM_SEL_MASK);
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reg |= OP_STR_DONE | op;
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core_writel(priv, reg, CORE_CFP_ACC);
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do {
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reg = core_readl(priv, CORE_CFP_ACC);
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if (!(reg & OP_STR_DONE))
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break;
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cpu_relax();
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} while (timeout--);
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if (!timeout)
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return -ETIMEDOUT;
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return 0;
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}
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static inline void bcm_sf2_cfp_rule_addr_set(struct bcm_sf2_priv *priv,
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unsigned int addr)
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{
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u32 reg;
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WARN_ON(addr >= CFP_NUM_RULES);
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reg = core_readl(priv, CORE_CFP_ACC);
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reg &= ~(XCESS_ADDR_MASK << XCESS_ADDR_SHIFT);
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reg |= addr << XCESS_ADDR_SHIFT;
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core_writel(priv, reg, CORE_CFP_ACC);
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}
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static inline unsigned int bcm_sf2_cfp_rule_size(struct bcm_sf2_priv *priv)
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{
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/* Entry #0 is reserved */
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return CFP_NUM_RULES - 1;
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}
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static int bcm_sf2_cfp_rule_set(struct dsa_switch *ds, int port,
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struct ethtool_rx_flow_spec *fs)
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{
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struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
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struct ethtool_tcpip4_spec *v4_spec;
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const struct cfp_udf_layout *layout;
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unsigned int slice_num, rule_index;
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unsigned int queue_num, port_num;
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u8 ip_proto, ip_frag;
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u8 num_udf;
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u32 reg;
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int ret;
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/* Check for unsupported extensions */
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if ((fs->flow_type & FLOW_EXT) &&
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(fs->m_ext.vlan_etype || fs->m_ext.data[1]))
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return -EINVAL;
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if (fs->location != RX_CLS_LOC_ANY &&
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test_bit(fs->location, priv->cfp.used))
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return -EBUSY;
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if (fs->location != RX_CLS_LOC_ANY &&
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fs->location > bcm_sf2_cfp_rule_size(priv))
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return -EINVAL;
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ip_frag = be32_to_cpu(fs->m_ext.data[0]);
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/* We do not support discarding packets, check that the
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* destination port is enabled and that we are within the
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* number of ports supported by the switch
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*/
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port_num = fs->ring_cookie / 8;
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if (fs->ring_cookie == RX_CLS_FLOW_DISC ||
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!(BIT(port_num) & ds->enabled_port_mask) ||
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port_num >= priv->hw_params.num_ports)
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return -EINVAL;
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switch (fs->flow_type & ~FLOW_EXT) {
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case TCP_V4_FLOW:
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ip_proto = IPPROTO_TCP;
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v4_spec = &fs->h_u.tcp_ip4_spec;
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break;
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case UDP_V4_FLOW:
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ip_proto = IPPROTO_UDP;
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v4_spec = &fs->h_u.udp_ip4_spec;
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break;
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default:
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return -EINVAL;
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}
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/* We only use one UDF slice for now */
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slice_num = 1;
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layout = &udf_tcpip4_layout;
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num_udf = bcm_sf2_get_num_udf_slices(layout->slices);
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/* Apply the UDF layout for this filter */
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bcm_sf2_cfp_udf_set(priv, slice_num, layout->slices);
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/* Apply to all packets received through this port */
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core_writel(priv, BIT(port), CORE_CFP_DATA_PORT(7));
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/* S-Tag status [31:30]
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* C-Tag status [29:28]
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* L2 framing [27:26]
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* L3 framing [25:24]
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* IP ToS [23:16]
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* IP proto [15:08]
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* IP Fragm [7]
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* Non 1st frag [6]
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* IP Authen [5]
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* TTL range [4:3]
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* PPPoE session [2]
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* Reserved [1]
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* UDF_Valid[8] [0]
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*/
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core_writel(priv, v4_spec->tos << 16 | ip_proto << 8 | ip_frag << 7,
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CORE_CFP_DATA_PORT(6));
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/* UDF_Valid[7:0] [31:24]
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* S-Tag [23:8]
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* C-Tag [7:0]
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*/
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core_writel(priv, GENMASK(num_udf - 1, 0) << 24, CORE_CFP_DATA_PORT(5));
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/* C-Tag [31:24]
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* UDF_n_A8 [23:8]
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* UDF_n_A7 [7:0]
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*/
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core_writel(priv, 0, CORE_CFP_DATA_PORT(4));
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/* UDF_n_A7 [31:24]
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* UDF_n_A6 [23:8]
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* UDF_n_A5 [7:0]
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*/
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core_writel(priv, be16_to_cpu(v4_spec->pdst) >> 8,
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CORE_CFP_DATA_PORT(3));
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/* UDF_n_A5 [31:24]
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* UDF_n_A4 [23:8]
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* UDF_n_A3 [7:0]
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*/
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reg = (be16_to_cpu(v4_spec->pdst) & 0xff) << 24 |
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(u32)be16_to_cpu(v4_spec->psrc) << 8 |
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(be32_to_cpu(v4_spec->ip4dst) & 0x0000ff00) >> 8;
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core_writel(priv, reg, CORE_CFP_DATA_PORT(2));
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/* UDF_n_A3 [31:24]
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* UDF_n_A2 [23:8]
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* UDF_n_A1 [7:0]
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*/
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reg = (u32)(be32_to_cpu(v4_spec->ip4dst) & 0xff) << 24 |
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(u32)(be32_to_cpu(v4_spec->ip4dst) >> 16) << 8 |
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(be32_to_cpu(v4_spec->ip4src) & 0x0000ff00) >> 8;
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core_writel(priv, reg, CORE_CFP_DATA_PORT(1));
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/* UDF_n_A1 [31:24]
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* UDF_n_A0 [23:8]
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* Reserved [7:4]
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* Slice ID [3:2]
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* Slice valid [1:0]
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*/
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reg = (u32)(be32_to_cpu(v4_spec->ip4src) & 0xff) << 24 |
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(u32)(be32_to_cpu(v4_spec->ip4src) >> 16) << 8 |
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SLICE_NUM(slice_num) | SLICE_VALID;
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core_writel(priv, reg, CORE_CFP_DATA_PORT(0));
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/* Source port map match */
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core_writel(priv, 0xff, CORE_CFP_MASK_PORT(7));
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/* Mask with the specific layout for IPv4 packets */
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core_writel(priv, layout->mask_value, CORE_CFP_MASK_PORT(6));
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/* Mask all but valid UDFs */
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core_writel(priv, GENMASK(num_udf - 1, 0) << 24, CORE_CFP_MASK_PORT(5));
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/* Mask all */
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core_writel(priv, 0, CORE_CFP_MASK_PORT(4));
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/* All other UDFs should be matched with the filter */
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core_writel(priv, 0xff, CORE_CFP_MASK_PORT(3));
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core_writel(priv, 0xffffffff, CORE_CFP_MASK_PORT(2));
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core_writel(priv, 0xffffffff, CORE_CFP_MASK_PORT(1));
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core_writel(priv, 0xffffff0f, CORE_CFP_MASK_PORT(0));
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/* Locate the first rule available */
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if (fs->location == RX_CLS_LOC_ANY)
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rule_index = find_first_zero_bit(priv->cfp.used,
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bcm_sf2_cfp_rule_size(priv));
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else
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rule_index = fs->location;
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/* Insert into TCAM now */
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bcm_sf2_cfp_rule_addr_set(priv, rule_index);
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ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | TCAM_SEL);
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if (ret) {
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pr_err("TCAM entry at addr %d failed\n", rule_index);
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return ret;
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}
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/* Replace ARL derived destination with DST_MAP derived, define
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* which port and queue this should be forwarded to.
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*
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* We have a small oddity where Port 6 just does not have a
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* valid bit here (so we subtract by one).
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*/
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queue_num = fs->ring_cookie % 8;
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if (port_num >= 7)
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port_num -= 1;
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reg = CHANGE_FWRD_MAP_IB_REP_ARL | BIT(port_num + DST_MAP_IB_SHIFT) |
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CHANGE_TC | queue_num << NEW_TC_SHIFT;
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core_writel(priv, reg, CORE_ACT_POL_DATA0);
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/* Set classification ID that needs to be put in Broadcom tag */
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core_writel(priv, rule_index << CHAIN_ID_SHIFT,
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CORE_ACT_POL_DATA1);
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core_writel(priv, 0, CORE_ACT_POL_DATA2);
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/* Configure policer RAM now */
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ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | ACT_POL_RAM);
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if (ret) {
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pr_err("Policer entry at %d failed\n", rule_index);
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return ret;
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}
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/* Disable the policer */
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core_writel(priv, POLICER_MODE_DISABLE, CORE_RATE_METER0);
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/* Now the rate meter */
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ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | RATE_METER_RAM);
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if (ret) {
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pr_err("Meter entry at %d failed\n", rule_index);
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return ret;
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}
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/* Turn on CFP for this rule now */
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reg = core_readl(priv, CORE_CFP_CTL_REG);
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reg |= BIT(port);
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core_writel(priv, reg, CORE_CFP_CTL_REG);
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/* Flag the rule as being used and return it */
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set_bit(rule_index, priv->cfp.used);
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fs->location = rule_index;
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return 0;
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}
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static int bcm_sf2_cfp_rule_del(struct bcm_sf2_priv *priv, int port,
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u32 loc)
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{
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int ret;
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u32 reg;
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/* Refuse deletion of unused rules, and the default reserved rule */
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if (!test_bit(loc, priv->cfp.used) || loc == 0)
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return -EINVAL;
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/* Indicate which rule we want to read */
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bcm_sf2_cfp_rule_addr_set(priv, loc);
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ret = bcm_sf2_cfp_op(priv, OP_SEL_READ | TCAM_SEL);
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if (ret)
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return ret;
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/* Clear its valid bits */
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reg = core_readl(priv, CORE_CFP_DATA_PORT(0));
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reg &= ~SLICE_VALID;
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core_writel(priv, reg, CORE_CFP_DATA_PORT(0));
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/* Write back this entry into the TCAM now */
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ret = bcm_sf2_cfp_op(priv, OP_SEL_WRITE | TCAM_SEL);
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if (ret)
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return ret;
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clear_bit(loc, priv->cfp.used);
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return 0;
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}
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static void bcm_sf2_invert_masks(struct ethtool_rx_flow_spec *flow)
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{
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unsigned int i;
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for (i = 0; i < sizeof(flow->m_u); i++)
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flow->m_u.hdata[i] ^= 0xff;
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flow->m_ext.vlan_etype ^= cpu_to_be16(~0);
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flow->m_ext.vlan_tci ^= cpu_to_be16(~0);
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flow->m_ext.data[0] ^= cpu_to_be32(~0);
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flow->m_ext.data[1] ^= cpu_to_be32(~0);
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}
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static int bcm_sf2_cfp_rule_get(struct bcm_sf2_priv *priv, int port,
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struct ethtool_rxnfc *nfc, bool search)
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{
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struct ethtool_tcpip4_spec *v4_spec;
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unsigned int queue_num;
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u16 src_dst_port;
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u32 reg, ipv4;
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int ret;
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if (!search) {
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bcm_sf2_cfp_rule_addr_set(priv, nfc->fs.location);
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ret = bcm_sf2_cfp_op(priv, OP_SEL_READ | ACT_POL_RAM);
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if (ret)
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return ret;
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reg = core_readl(priv, CORE_ACT_POL_DATA0);
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ret = bcm_sf2_cfp_op(priv, OP_SEL_READ | TCAM_SEL);
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if (ret)
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return ret;
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} else {
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reg = core_readl(priv, CORE_ACT_POL_DATA0);
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}
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/* Extract the destination port */
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nfc->fs.ring_cookie = fls((reg >> DST_MAP_IB_SHIFT) &
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DST_MAP_IB_MASK) - 1;
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/* There is no Port 6, so we compensate for that here */
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if (nfc->fs.ring_cookie >= 6)
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nfc->fs.ring_cookie++;
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nfc->fs.ring_cookie *= 8;
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/* Extract the destination queue */
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queue_num = (reg >> NEW_TC_SHIFT) & NEW_TC_MASK;
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nfc->fs.ring_cookie += queue_num;
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/* Extract the IP protocol */
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reg = core_readl(priv, CORE_CFP_DATA_PORT(6));
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switch ((reg & IPPROTO_MASK) >> IPPROTO_SHIFT) {
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case IPPROTO_TCP:
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nfc->fs.flow_type = TCP_V4_FLOW;
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v4_spec = &nfc->fs.h_u.tcp_ip4_spec;
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break;
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case IPPROTO_UDP:
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nfc->fs.flow_type = UDP_V4_FLOW;
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v4_spec = &nfc->fs.h_u.udp_ip4_spec;
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break;
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default:
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/* Clear to exit the search process */
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if (search)
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core_readl(priv, CORE_CFP_DATA_PORT(7));
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return -EINVAL;
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}
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v4_spec->tos = (reg >> 16) & IPPROTO_MASK;
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nfc->fs.m_ext.data[0] = cpu_to_be32((reg >> 7) & 1);
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reg = core_readl(priv, CORE_CFP_DATA_PORT(3));
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/* src port [15:8] */
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src_dst_port = reg << 8;
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reg = core_readl(priv, CORE_CFP_DATA_PORT(2));
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/* src port [7:0] */
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src_dst_port |= (reg >> 24);
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v4_spec->pdst = cpu_to_be16(src_dst_port);
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nfc->fs.m_u.tcp_ip4_spec.pdst = cpu_to_be16(~0);
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v4_spec->psrc = cpu_to_be16((u16)(reg >> 8));
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nfc->fs.m_u.tcp_ip4_spec.psrc = cpu_to_be16(~0);
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/* IPv4 dst [15:8] */
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ipv4 = (reg & 0xff) << 8;
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reg = core_readl(priv, CORE_CFP_DATA_PORT(1));
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/* IPv4 dst [31:16] */
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ipv4 |= ((reg >> 8) & 0xffff) << 16;
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/* IPv4 dst [7:0] */
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ipv4 |= (reg >> 24) & 0xff;
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v4_spec->ip4dst = cpu_to_be32(ipv4);
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nfc->fs.m_u.tcp_ip4_spec.ip4dst = cpu_to_be32(~0);
|
|
|
|
/* IPv4 src [15:8] */
|
|
ipv4 = (reg & 0xff) << 8;
|
|
reg = core_readl(priv, CORE_CFP_DATA_PORT(0));
|
|
|
|
if (!(reg & SLICE_VALID))
|
|
return -EINVAL;
|
|
|
|
/* IPv4 src [7:0] */
|
|
ipv4 |= (reg >> 24) & 0xff;
|
|
/* IPv4 src [31:16] */
|
|
ipv4 |= ((reg >> 8) & 0xffff) << 16;
|
|
v4_spec->ip4src = cpu_to_be32(ipv4);
|
|
nfc->fs.m_u.tcp_ip4_spec.ip4src = cpu_to_be32(~0);
|
|
|
|
/* Read last to avoid next entry clobbering the results during search
|
|
* operations
|
|
*/
|
|
reg = core_readl(priv, CORE_CFP_DATA_PORT(7));
|
|
if (!(reg & 1 << port))
|
|
return -EINVAL;
|
|
|
|
bcm_sf2_invert_masks(&nfc->fs);
|
|
|
|
/* Put the TCAM size here */
|
|
nfc->data = bcm_sf2_cfp_rule_size(priv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* We implement the search doing a TCAM search operation */
|
|
static int bcm_sf2_cfp_rule_get_all(struct bcm_sf2_priv *priv,
|
|
int port, struct ethtool_rxnfc *nfc,
|
|
u32 *rule_locs)
|
|
{
|
|
unsigned int index = 1, rules_cnt = 0;
|
|
int ret;
|
|
u32 reg;
|
|
|
|
/* Do not poll on OP_STR_DONE to be self-clearing for search
|
|
* operations, we cannot use bcm_sf2_cfp_op here because it completes
|
|
* on clearing OP_STR_DONE which won't clear until the entire search
|
|
* operation is over.
|
|
*/
|
|
reg = core_readl(priv, CORE_CFP_ACC);
|
|
reg &= ~(XCESS_ADDR_MASK << XCESS_ADDR_SHIFT);
|
|
reg |= index << XCESS_ADDR_SHIFT;
|
|
reg &= ~(OP_SEL_MASK | RAM_SEL_MASK);
|
|
reg |= OP_SEL_SEARCH | TCAM_SEL | OP_STR_DONE;
|
|
core_writel(priv, reg, CORE_CFP_ACC);
|
|
|
|
do {
|
|
/* Wait for results to be ready */
|
|
reg = core_readl(priv, CORE_CFP_ACC);
|
|
|
|
/* Extract the address we are searching */
|
|
index = reg >> XCESS_ADDR_SHIFT;
|
|
index &= XCESS_ADDR_MASK;
|
|
|
|
/* We have a valid search result, so flag it accordingly */
|
|
if (reg & SEARCH_STS) {
|
|
ret = bcm_sf2_cfp_rule_get(priv, port, nfc, true);
|
|
if (ret)
|
|
continue;
|
|
|
|
rule_locs[rules_cnt] = index;
|
|
rules_cnt++;
|
|
}
|
|
|
|
/* Search is over break out */
|
|
if (!(reg & OP_STR_DONE))
|
|
break;
|
|
|
|
} while (index < CFP_NUM_RULES);
|
|
|
|
/* Put the TCAM size here */
|
|
nfc->data = bcm_sf2_cfp_rule_size(priv);
|
|
nfc->rule_cnt = rules_cnt;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int bcm_sf2_get_rxnfc(struct dsa_switch *ds, int port,
|
|
struct ethtool_rxnfc *nfc, u32 *rule_locs)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
int ret = 0;
|
|
|
|
mutex_lock(&priv->cfp.lock);
|
|
|
|
switch (nfc->cmd) {
|
|
case ETHTOOL_GRXCLSRLCNT:
|
|
/* Subtract the default, unusable rule */
|
|
nfc->rule_cnt = bitmap_weight(priv->cfp.used,
|
|
CFP_NUM_RULES) - 1;
|
|
/* We support specifying rule locations */
|
|
nfc->data |= RX_CLS_LOC_SPECIAL;
|
|
break;
|
|
case ETHTOOL_GRXCLSRULE:
|
|
ret = bcm_sf2_cfp_rule_get(priv, port, nfc, false);
|
|
break;
|
|
case ETHTOOL_GRXCLSRLALL:
|
|
ret = bcm_sf2_cfp_rule_get_all(priv, port, nfc, rule_locs);
|
|
break;
|
|
default:
|
|
ret = -EOPNOTSUPP;
|
|
break;
|
|
}
|
|
|
|
mutex_unlock(&priv->cfp.lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int bcm_sf2_set_rxnfc(struct dsa_switch *ds, int port,
|
|
struct ethtool_rxnfc *nfc)
|
|
{
|
|
struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
|
|
int ret = 0;
|
|
|
|
mutex_lock(&priv->cfp.lock);
|
|
|
|
switch (nfc->cmd) {
|
|
case ETHTOOL_SRXCLSRLINS:
|
|
ret = bcm_sf2_cfp_rule_set(ds, port, &nfc->fs);
|
|
break;
|
|
|
|
case ETHTOOL_SRXCLSRLDEL:
|
|
ret = bcm_sf2_cfp_rule_del(priv, port, nfc->fs.location);
|
|
break;
|
|
default:
|
|
ret = -EOPNOTSUPP;
|
|
break;
|
|
}
|
|
|
|
mutex_unlock(&priv->cfp.lock);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int bcm_sf2_cfp_rst(struct bcm_sf2_priv *priv)
|
|
{
|
|
unsigned int timeout = 1000;
|
|
u32 reg;
|
|
|
|
reg = core_readl(priv, CORE_CFP_ACC);
|
|
reg |= TCAM_RESET;
|
|
core_writel(priv, reg, CORE_CFP_ACC);
|
|
|
|
do {
|
|
reg = core_readl(priv, CORE_CFP_ACC);
|
|
if (!(reg & TCAM_RESET))
|
|
break;
|
|
|
|
cpu_relax();
|
|
} while (timeout--);
|
|
|
|
if (!timeout)
|
|
return -ETIMEDOUT;
|
|
|
|
return 0;
|
|
}
|