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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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1306c08a7c
In order to handle errata I688, a page of sram was reserved by doing a static iotable map. Now that we use gen_pool to manage sram, we can completely remove all of these static mappings and use gen_pool_alloc() to get the one page of sram space needed to implement errata I688. omap_bus_sync will be NOP until SRAM initialization happens. Suggested-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Rajendra Nayak <rnayak@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
77 lines
2.5 KiB
C
77 lines
2.5 KiB
C
/*
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* Interface for functions that need to be run in internal SRAM
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASSEMBLY__
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#include <plat/sram.h>
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extern void omap2_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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u32 base_cs, u32 force_unlock);
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extern void omap2_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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u32 mem_type);
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extern u32 omap2_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val, int bypass);
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extern u32 omap3_configure_core_dpll(
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u32 m2, u32 unlock_dll, u32 f, u32 inc,
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u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
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extern void omap3_sram_restore_context(void);
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/* Do not use these */
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extern void omap24xx_sram_reprogram_clock(u32 ckctl, u32 dpllctl);
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extern unsigned long omap24xx_sram_reprogram_clock_sz;
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extern void omap242x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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u32 base_cs, u32 force_unlock);
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extern unsigned long omap242x_sram_ddr_init_sz;
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extern u32 omap242x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
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int bypass);
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extern unsigned long omap242x_sram_set_prcm_sz;
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extern void omap242x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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u32 mem_type);
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extern unsigned long omap242x_sram_reprogram_sdrc_sz;
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extern void omap243x_sram_ddr_init(u32 *slow_dll_ctrl, u32 fast_dll_ctrl,
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u32 base_cs, u32 force_unlock);
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extern unsigned long omap243x_sram_ddr_init_sz;
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extern u32 omap243x_sram_set_prcm(u32 dpll_ctrl_val, u32 sdrc_rfr_val,
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int bypass);
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extern unsigned long omap243x_sram_set_prcm_sz;
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extern void omap243x_sram_reprogram_sdrc(u32 perf_level, u32 dll_val,
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u32 mem_type);
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extern unsigned long omap243x_sram_reprogram_sdrc_sz;
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extern u32 omap3_sram_configure_core_dpll(
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u32 m2, u32 unlock_dll, u32 f, u32 inc,
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u32 sdrc_rfr_ctrl_0, u32 sdrc_actim_ctrl_a_0,
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u32 sdrc_actim_ctrl_b_0, u32 sdrc_mr_0,
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u32 sdrc_rfr_ctrl_1, u32 sdrc_actim_ctrl_a_1,
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u32 sdrc_actim_ctrl_b_1, u32 sdrc_mr_1);
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extern unsigned long omap3_sram_configure_core_dpll_sz;
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#ifdef CONFIG_PM
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extern void omap_push_sram_idle(void);
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#else
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static inline void omap_push_sram_idle(void) {}
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#endif /* CONFIG_PM */
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#endif /* __ASSEMBLY__ */
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/*
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* OMAP2+: define the SRAM PA addresses.
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* Used by the SRAM management code and the idle sleep code.
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*/
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#define OMAP2_SRAM_PA 0x40200000
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#define OMAP3_SRAM_PA 0x40200000
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