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b765234e72
Prior to this patch we were using a hardcoded RGMII TX clock delay of 2ns (= 1/4 cycle of the 125MHz RGMII TX clock). This value works for many boards, but unfortunately not for all (due to the way the actual circuit is designed, sometimes because the TX delay is enabled in the PHY, etc.). Making the TX delay on the MAC side configurable allows us to support all possible hardware combinations. This allows fixing a compatibility issue on some boards, where the RTL8211F PHY is configured to generate the TX delay. We can now turn off the TX delay in the MAC, because otherwise we would be applying the delay twice (which results in non-working TX traffic). Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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3com | ||
8390 | ||
adaptec | ||
adi | ||
aeroflex | ||
agere | ||
alacritech | ||
allwinner | ||
alteon | ||
altera | ||
amazon | ||
amd | ||
apm | ||
apple | ||
arc | ||
atheros | ||
aurora | ||
broadcom | ||
brocade | ||
cadence | ||
calxeda | ||
cavium | ||
chelsio | ||
cirrus | ||
cisco | ||
davicom | ||
dec | ||
dlink | ||
emulex | ||
ezchip | ||
faraday | ||
freescale | ||
fujitsu | ||
hisilicon | ||
hp | ||
i825xx | ||
ibm | ||
intel | ||
marvell | ||
mediatek | ||
mellanox | ||
micrel | ||
microchip | ||
moxa | ||
myricom | ||
natsemi | ||
neterion | ||
netronome | ||
nuvoton | ||
nvidia | ||
nxp | ||
oki-semi | ||
packetengines | ||
pasemi | ||
qlogic | ||
qualcomm | ||
rdc | ||
realtek | ||
renesas | ||
rocker | ||
samsung | ||
seeq | ||
sfc | ||
sgi | ||
silan | ||
sis | ||
smsc | ||
stmicro | ||
sun | ||
tehuti | ||
ti | ||
tile | ||
toshiba | ||
tundra | ||
via | ||
wiznet | ||
xilinx | ||
xircom | ||
xscale | ||
dnet.c | ||
dnet.h | ||
ec_bhf.c | ||
ethoc.c | ||
fealnx.c | ||
jme.c | ||
jme.h | ||
Kconfig | ||
korina.c | ||
lantiq_etop.c | ||
Makefile | ||
netx-eth.c |