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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c501d0b149
Add implementation for: - pin control, group information retrieval: count, name and pins - pin muxing: - function information (count, name and groups) - mux setting - gpio control (enable, disable, set direction) - pin configuration: - pull disable - pull up/down and pull strength - debounce - any other option is treated as not supported. Signed-off-by: Cristina Ciocan <cristina.ciocan@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
56 lines
1.5 KiB
Plaintext
56 lines
1.5 KiB
Plaintext
#
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# Intel pin control drivers
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#
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config PINCTRL_BAYTRAIL
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bool "Intel Baytrail GPIO pin control"
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depends on GPIOLIB && ACPI
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select GPIOLIB_IRQCHIP
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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help
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driver for memory mapped GPIO functionality on Intel Baytrail
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platforms. Supports 3 banks with 102, 28 and 44 gpios.
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Most pins are usually muxed to some other functionality by firmware,
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so only a small amount is available for gpio use.
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Requires ACPI device enumeration code to set up a platform device.
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config PINCTRL_CHERRYVIEW
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tristate "Intel Cherryview/Braswell pinctrl and GPIO driver"
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depends on ACPI
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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help
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Cherryview/Braswell pinctrl driver provides an interface that
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allows configuring of SoC pins and using them as GPIOs.
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config PINCTRL_INTEL
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tristate
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select PINMUX
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select PINCONF
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select GENERIC_PINCONF
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select GPIOLIB
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select GPIOLIB_IRQCHIP
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config PINCTRL_BROXTON
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tristate "Intel Broxton pinctrl and GPIO driver"
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depends on ACPI
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select PINCTRL_INTEL
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help
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Broxton pinctrl driver provides an interface that allows
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configuring of SoC pins and using them as GPIOs.
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config PINCTRL_SUNRISEPOINT
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tristate "Intel Sunrisepoint pinctrl and GPIO driver"
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depends on ACPI
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select PINCTRL_INTEL
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help
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Sunrisepoint is the PCH of Intel Skylake. This pinctrl driver
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provides an interface that allows configuring of PCH pins and
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using them as GPIOs.
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