Christoph Hellwig b733116fea unicore32: remove swiotlb support ... unicore32 is a bog standard 32-bit port without larger physical address space, highmem or any other obvious addressing limitation. There should be no need to bounce buffer using swiotlb. Signed-off-by: Christoph Hellwig <hch@lst.de> Acked-by: Guan Xuetao <gxt@pku.edu.cn>		2018-09-30 16:07:35 -07:00
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alignment.c	sched/headers: Prepare for new header dependencies before moving code to <linux/sched/debug.h>	2017-03-02 08:42:34 +01:00
cache-ucv2.S	unicore32 core architecture: mm related: consistent device DMA handling	2011-03-17 09:19:09 +08:00
extable.c	unicore32: migrate exception table users off module.h and onto extable.h	2017-01-26 10:58:18 -05:00
fault.c	mm: convert return type of handle_mm_fault() caller to vm_fault_t	2018-08-17 16:20:28 -07:00
flush.c	mm: fix races between swapoff and flush dcache	2018-04-05 21:36:26 -07:00
init.c	unicore32: remove swiotlb support	2018-09-30 16:07:35 -07:00
ioremap.c	arch/unicore32/mm/ioremap.c: return NULL on invalid pfn	2014-06-04 16:53:53 -07:00
Kconfig	swiotlb: move the SWIOTLB config symbol to lib/Kconfig	2018-05-09 06:58:01 +02:00
Makefile	unicore32: use generic swiotlb_ops	2018-01-15 09:35:55 +01:00
mm.h	Disintegrate asm/system.h for Unicore32 [based on ver #3, changed by gxt]	2012-03-28 18:30:03 +01:00
mmu.c	mm: fix races between swapoff and flush dcache	2018-04-05 21:36:26 -07:00
pgd.c	mm: introduce wrappers to access mm->nr_ptes	2017-11-15 18:21:04 -08:00
proc-macros.S	unicore32 core architecture: processor and system headers	2011-03-17 09:19:06 +08:00
proc-syms.c	unicore32: make dma_cache_sync a no-op	2017-10-19 16:37:36 +02:00
proc-ucv2.S	unicore32 core architecture: processor and system headers	2011-03-17 09:19:06 +08:00
tlb-ucv2.S	unicore32 core architecture: mm related: consistent device DMA handling	2011-03-17 09:19:09 +08:00