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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b6e23bb63f
There is ~10% possibility that the following emergency restart command
fails to reboot imx6q.
$ echo b > /proc/sysrq-trigger
The IMX restart routine mxc_restart() assumes that it will always run on
primary core, and will call imx_src_prepare_restart() to disable
secondary cores in order to get them come to online in the following
boot. However, the assumption is only true for normal kernel_restart()
case where migrate_to_reboot_cpu() will be called to migrate to primary
core, but not necessarily true for emergency_restart() case. So when
emergency_restart() calls into mxc_restart() on any secondary core,
system will hang immediately once imx_src_prepare_restart() is called
to disabled secondary cores. Since emergency_restart() is defined as a
function that is safe to call in interrupt context, we cannot just call
migrate_to_reboot_cpu() to fix the issue.
Fortunately, we just found that the issue can be fixed at imx6q platform
level. We used to call imx_src_prepare_restart() to disable all
secondary cores before resetting hardware. Otherwise, the secondary
will fail come to online in the reboot. However, we recently found that
after commit 6050d18 (ARM: imx: reset core along with enable/disable
operation) comes to play, we do not need to reset the secondary cores
any more. That said, mxc_restart() now can run on any core to reboot
the system, as long as we remove the imx_src_prepare_restart() call from
mxc_restart().
So let's simply remove imx_src_prepare_restart() call to fix the above
emergency restart failure.
Reported-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
144 lines
3.6 KiB
C
144 lines
3.6 KiB
C
/*
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* Copyright (C) 1999 ARM Limited
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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* Copyright 2006-2007 Freescale Semiconductor, Inc. All Rights Reserved.
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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* Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/clk.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <asm/system_misc.h>
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#include <asm/proc-fns.h>
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#include <asm/mach-types.h>
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#include <asm/hardware/cache-l2x0.h>
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#include "common.h"
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#include "hardware.h"
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static void __iomem *wdog_base;
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static struct clk *wdog_clk;
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/*
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* Reset the system. It is called by machine_restart().
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*/
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void mxc_restart(enum reboot_mode mode, const char *cmd)
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{
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unsigned int wcr_enable;
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if (wdog_clk)
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clk_enable(wdog_clk);
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if (cpu_is_mx1())
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wcr_enable = (1 << 0);
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else
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wcr_enable = (1 << 2);
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/* Assert SRS signal */
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__raw_writew(wcr_enable, wdog_base);
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/* write twice to ensure the request will not get ignored */
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__raw_writew(wcr_enable, wdog_base);
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/* wait for reset to assert... */
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mdelay(500);
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pr_err("%s: Watchdog reset failed to assert reset\n", __func__);
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/* delay to allow the serial port to show the message */
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mdelay(50);
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/* we'll take a jump through zero as a poor second */
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soft_restart(0);
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}
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void __init mxc_arch_reset_init(void __iomem *base)
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{
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wdog_base = base;
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wdog_clk = clk_get_sys("imx2-wdt.0", NULL);
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if (IS_ERR(wdog_clk)) {
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pr_warn("%s: failed to get wdog clock\n", __func__);
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wdog_clk = NULL;
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return;
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}
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clk_prepare(wdog_clk);
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}
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void __init mxc_arch_reset_init_dt(void)
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{
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struct device_node *np;
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np = of_find_compatible_node(NULL, NULL, "fsl,imx21-wdt");
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wdog_base = of_iomap(np, 0);
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WARN_ON(!wdog_base);
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wdog_clk = of_clk_get(np, 0);
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if (IS_ERR(wdog_clk)) {
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pr_warn("%s: failed to get wdog clock\n", __func__);
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wdog_clk = NULL;
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return;
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}
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clk_prepare(wdog_clk);
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}
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#ifdef CONFIG_CACHE_L2X0
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void __init imx_init_l2cache(void)
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{
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void __iomem *l2x0_base;
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struct device_node *np;
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unsigned int val;
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np = of_find_compatible_node(NULL, NULL, "arm,pl310-cache");
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if (!np)
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goto out;
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l2x0_base = of_iomap(np, 0);
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if (!l2x0_base) {
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of_node_put(np);
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goto out;
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}
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/* Configure the L2 PREFETCH and POWER registers */
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val = readl_relaxed(l2x0_base + L2X0_PREFETCH_CTRL);
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val |= 0x70800000;
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/*
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* The L2 cache controller(PL310) version on the i.MX6D/Q is r3p1-50rel0
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* The L2 cache controller(PL310) version on the i.MX6DL/SOLO/SL is r3p2
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* But according to ARM PL310 errata: 752271
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* ID: 752271: Double linefill feature can cause data corruption
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* Fault Status: Present in: r3p0, r3p1, r3p1-50rel0. Fixed in r3p2
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* Workaround: The only workaround to this erratum is to disable the
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* double linefill feature. This is the default behavior.
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*/
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if (cpu_is_imx6q())
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val &= ~(1 << 30 | 1 << 23);
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writel_relaxed(val, l2x0_base + L2X0_PREFETCH_CTRL);
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val = L2X0_DYNAMIC_CLK_GATING_EN | L2X0_STNDBY_MODE_EN;
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writel_relaxed(val, l2x0_base + L2X0_POWER_CTRL);
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iounmap(l2x0_base);
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of_node_put(np);
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out:
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l2x0_of_init(0, ~0UL);
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}
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#endif
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