mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 19:57:00 +07:00
b24413180f
Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
377 lines
8.8 KiB
ArmAsm
377 lines
8.8 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* We need constants.h for:
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* VMA_VM_MM
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* VMA_VM_FLAGS
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* VM_EXEC
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*/
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#include <asm/asm-offsets.h>
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#include <asm/thread_info.h>
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#ifdef CONFIG_CPU_V7M
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#include <asm/v7m.h>
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#endif
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/*
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* vma_vm_mm - get mm pointer from vma pointer (vma->vm_mm)
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*/
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.macro vma_vm_mm, rd, rn
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ldr \rd, [\rn, #VMA_VM_MM]
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.endm
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/*
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* vma_vm_flags - get vma->vm_flags
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*/
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.macro vma_vm_flags, rd, rn
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ldr \rd, [\rn, #VMA_VM_FLAGS]
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.endm
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/*
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* act_mm - get current->active_mm
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*/
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.macro act_mm, rd
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bic \rd, sp, #8128
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bic \rd, \rd, #63
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ldr \rd, [\rd, #TI_TASK]
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.if (TSK_ACTIVE_MM > IMM12_MASK)
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add \rd, \rd, #TSK_ACTIVE_MM & ~IMM12_MASK
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.endif
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ldr \rd, [\rd, #TSK_ACTIVE_MM & IMM12_MASK]
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.endm
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/*
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* mmid - get context id from mm pointer (mm->context.id)
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* note, this field is 64bit, so in big-endian the two words are swapped too.
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*/
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.macro mmid, rd, rn
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#ifdef __ARMEB__
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ldr \rd, [\rn, #MM_CONTEXT_ID + 4 ]
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#else
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ldr \rd, [\rn, #MM_CONTEXT_ID]
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#endif
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.endm
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/*
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* mask_asid - mask the ASID from the context ID
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*/
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.macro asid, rd, rn
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and \rd, \rn, #255
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.endm
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.macro crval, clear, mmuset, ucset
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#ifdef CONFIG_MMU
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.word \clear
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.word \mmuset
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#else
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.word \clear
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.word \ucset
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#endif
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.endm
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/*
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* dcache_line_size - get the minimum D-cache line size from the CTR register
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* on ARMv7.
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*/
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.macro dcache_line_size, reg, tmp
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#ifdef CONFIG_CPU_V7M
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movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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ldr \tmp, [\tmp]
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#else
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mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
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#endif
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lsr \tmp, \tmp, #16
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and \tmp, \tmp, #0xf @ cache line size encoding
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mov \reg, #4 @ bytes per word
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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/*
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* icache_line_size - get the minimum I-cache line size from the CTR register
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* on ARMv7.
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*/
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.macro icache_line_size, reg, tmp
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#ifdef CONFIG_CPU_V7M
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movw \tmp, #:lower16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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movt \tmp, #:upper16:BASEADDR_V7M_SCB + V7M_SCB_CTR
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ldr \tmp, [\tmp]
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#else
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mrc p15, 0, \tmp, c0, c0, 1 @ read ctr
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#endif
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and \tmp, \tmp, #0xf @ cache line size encoding
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mov \reg, #4 @ bytes per word
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mov \reg, \reg, lsl \tmp @ actual cache line size
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.endm
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/*
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* Sanity check the PTE configuration for the code below - which makes
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* certain assumptions about how these bits are laid out.
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*/
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#ifdef CONFIG_MMU
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#if L_PTE_SHARED != PTE_EXT_SHARED
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#error PTE shared bit mismatch
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#endif
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#if !defined (CONFIG_ARM_LPAE) && \
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(L_PTE_XN+L_PTE_USER+L_PTE_RDONLY+L_PTE_DIRTY+L_PTE_YOUNG+\
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L_PTE_PRESENT) > L_PTE_SHARED
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#error Invalid Linux PTE bit settings
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#endif
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#endif /* CONFIG_MMU */
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/*
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* The ARMv6 and ARMv7 set_pte_ext translation function.
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*
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* Permission translation:
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* YUWD APX AP1 AP0 SVC User
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* 0xxx 0 0 0 no acc no acc
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* 100x 1 0 1 r/o no acc
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* 10x0 1 0 1 r/o no acc
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* 1011 0 0 1 r/w no acc
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* 110x 1 1 1 r/o r/o
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* 11x0 1 1 1 r/o r/o
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* 1111 0 1 1 r/w r/w
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*/
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.macro armv6_mt_table pfx
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\pfx\()_mt_table:
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.long 0x00 @ L_PTE_MT_UNCACHED
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.long PTE_EXT_TEX(1) @ L_PTE_MT_BUFFERABLE
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.long PTE_CACHEABLE @ L_PTE_MT_WRITETHROUGH
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEBACK
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.long PTE_BUFFERABLE @ L_PTE_MT_DEV_SHARED
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.long 0x00 @ unused
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.long 0x00 @ L_PTE_MT_MINICACHE (not present)
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.long PTE_EXT_TEX(1) | PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_WRITEALLOC
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.long 0x00 @ unused
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.long PTE_EXT_TEX(1) @ L_PTE_MT_DEV_WC
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE @ L_PTE_MT_DEV_CACHED
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.long PTE_EXT_TEX(2) @ L_PTE_MT_DEV_NONSHARED
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.long 0x00 @ unused
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.long 0x00 @ unused
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.long PTE_CACHEABLE | PTE_BUFFERABLE | PTE_EXT_APX @ L_PTE_MT_VECTORS
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.endm
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.macro armv6_set_pte_ext pfx
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str r1, [r0], #2048 @ linux version
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bic r3, r1, #0x000003fc
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bic r3, r3, #PTE_TYPE_MASK
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orr r3, r3, r2
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orr r3, r3, #PTE_EXT_AP0 | 2
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adr ip, \pfx\()_mt_table
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and r2, r1, #L_PTE_MT_MASK
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ldr r2, [ip, r2]
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eor r1, r1, #L_PTE_DIRTY
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tst r1, #L_PTE_DIRTY|L_PTE_RDONLY
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orrne r3, r3, #PTE_EXT_APX
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tst r1, #L_PTE_USER
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orrne r3, r3, #PTE_EXT_AP1
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tstne r3, #PTE_EXT_APX
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@ user read-only -> kernel read-only
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bicne r3, r3, #PTE_EXT_AP0
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tst r1, #L_PTE_XN
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orrne r3, r3, #PTE_EXT_XN
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eor r3, r3, r2
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tst r1, #L_PTE_YOUNG
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tstne r1, #L_PTE_PRESENT
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moveq r3, #0
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tstne r1, #L_PTE_NONE
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movne r3, #0
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str r3, [r0]
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mcr p15, 0, r0, c7, c10, 1 @ flush_pte
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.endm
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/*
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* The ARMv3, ARMv4 and ARMv5 set_pte_ext translation function,
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* covering most CPUs except Xscale and Xscale 3.
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*
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* Permission translation:
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* YUWD AP SVC User
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* 0xxx 0x00 no acc no acc
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* 100x 0x00 r/o no acc
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* 10x0 0x00 r/o no acc
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* 1011 0x55 r/w no acc
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* 110x 0xaa r/w r/o
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* 11x0 0xaa r/w r/o
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* 1111 0xff r/w r/w
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*/
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.macro armv3_set_pte_ext wc_disable=1
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str r1, [r0], #2048 @ linux version
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eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
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bic r2, r2, #PTE_TYPE_MASK
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orr r2, r2, #PTE_TYPE_SMALL
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tst r3, #L_PTE_USER @ user?
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orrne r2, r2, #PTE_SMALL_AP_URO_SRW
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tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
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orreq r2, r2, #PTE_SMALL_AP_UNO_SRW
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tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
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movne r2, #0
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.if \wc_disable
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#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
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tst r2, #PTE_CACHEABLE
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bicne r2, r2, #PTE_BUFFERABLE
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#endif
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.endif
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str r2, [r0] @ hardware version
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.endm
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/*
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* Xscale set_pte_ext translation, split into two halves to cope
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* with work-arounds. r3 must be preserved by code between these
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* two macros.
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*
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* Permission translation:
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* YUWD AP SVC User
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* 0xxx 00 no acc no acc
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* 100x 00 r/o no acc
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* 10x0 00 r/o no acc
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* 1011 01 r/w no acc
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* 110x 10 r/w r/o
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* 11x0 10 r/w r/o
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* 1111 11 r/w r/w
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*/
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.macro xscale_set_pte_ext_prologue
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str r1, [r0] @ linux version
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eor r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY
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bic r2, r1, #PTE_SMALL_AP_MASK @ keep C, B bits
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orr r2, r2, #PTE_TYPE_EXT @ extended page
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tst r3, #L_PTE_USER @ user?
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orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
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tst r3, #L_PTE_RDONLY | L_PTE_DIRTY @ write and dirty?
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orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
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@ combined with user -> user r/w
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.endm
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.macro xscale_set_pte_ext_epilogue
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tst r3, #L_PTE_PRESENT | L_PTE_YOUNG @ present and young?
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movne r2, #0 @ no -> fault
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str r2, [r0, #2048]! @ hardware version
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mov ip, #0
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mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
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mcr p15, 0, ip, c7, c10, 4 @ data write barrier
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.endm
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.macro define_processor_functions name:req, dabort:req, pabort:req, nommu=0, suspend=0
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.type \name\()_processor_functions, #object
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.align 2
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ENTRY(\name\()_processor_functions)
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.word \dabort
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.word \pabort
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.word cpu_\name\()_proc_init
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.word cpu_\name\()_proc_fin
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.word cpu_\name\()_reset
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.word cpu_\name\()_do_idle
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.word cpu_\name\()_dcache_clean_area
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.word cpu_\name\()_switch_mm
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.if \nommu
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.word 0
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.else
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.word cpu_\name\()_set_pte_ext
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.endif
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.if \suspend
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.word cpu_\name\()_suspend_size
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#ifdef CONFIG_ARM_CPU_SUSPEND
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.word cpu_\name\()_do_suspend
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.word cpu_\name\()_do_resume
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#else
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.word 0
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.word 0
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#endif
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.else
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.word 0
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.word 0
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.word 0
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.endif
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.size \name\()_processor_functions, . - \name\()_processor_functions
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.endm
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.macro define_cache_functions name:req
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.align 2
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.type \name\()_cache_fns, #object
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ENTRY(\name\()_cache_fns)
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.long \name\()_flush_icache_all
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.long \name\()_flush_kern_cache_all
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.long \name\()_flush_kern_cache_louis
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.long \name\()_flush_user_cache_all
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.long \name\()_flush_user_cache_range
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.long \name\()_coherent_kern_range
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.long \name\()_coherent_user_range
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.long \name\()_flush_kern_dcache_area
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.long \name\()_dma_map_area
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.long \name\()_dma_unmap_area
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.long \name\()_dma_flush_range
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.size \name\()_cache_fns, . - \name\()_cache_fns
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.endm
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.macro define_tlb_functions name:req, flags_up:req, flags_smp
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.type \name\()_tlb_fns, #object
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ENTRY(\name\()_tlb_fns)
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.long \name\()_flush_user_tlb_range
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.long \name\()_flush_kern_tlb_range
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.ifnb \flags_smp
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ALT_SMP(.long \flags_smp )
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ALT_UP(.long \flags_up )
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.else
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.long \flags_up
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.endif
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.size \name\()_tlb_fns, . - \name\()_tlb_fns
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.endm
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.macro globl_equ x, y
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.globl \x
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.equ \x, \y
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.endm
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.macro initfn, func, base
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.long \func - \base
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.endm
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/*
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* Macro to calculate the log2 size for the protection region
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* registers. This calculates rd = log2(size) - 1. tmp must
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* not be the same register as rd.
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*/
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.macro pr_sz, rd, size, tmp
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mov \tmp, \size, lsr #12
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mov \rd, #11
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1: movs \tmp, \tmp, lsr #1
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addne \rd, \rd, #1
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bne 1b
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.endm
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/*
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* Macro to generate a protection region register value
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* given a pre-masked address, size, and enable bit.
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* Corrupts size.
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*/
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.macro pr_val, dest, addr, size, enable
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pr_sz \dest, \size, \size @ calculate log2(size) - 1
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orr \dest, \addr, \dest, lsl #1 @ mask in the region size
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orr \dest, \dest, \enable
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.endm
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