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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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eebb3e8d8a
This is a third approach to workaround long standing issue with LPSS on BayTrail. First one [1] was reverted since it didn't resolve the issue comprehensively. Second one [2] was rejected by internal review. The LPSS DMA controller does not have neither _PS0 nor _PS3 method. Moreover it can be powered off automatically whenever the last LPSS device goes down. In case of no power any access to the DMA controller will hang the system. The behaviour is reproduced on some HP laptops based on Intel BayTrail [3,4] as well as on ASuS T100TA transformer. Power on the LPSS island through the registers accessible in a specific way. [1] http://www.spinics.net/lists/linux-acpi/msg53963.html [2] https://bugzilla.redhat.com/attachment.cgi?id=1066779&action=diff [3] https://bugzilla.redhat.com/show_bug.cgi?id=1184273 [4] http://www.spinics.net/lists/dmaengine/msg01514.html Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
121 lines
2.9 KiB
C
121 lines
2.9 KiB
C
/*
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* Intel OnChip System Fabric MailBox access support
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*/
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#ifndef IOSF_MBI_SYMS_H
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#define IOSF_MBI_SYMS_H
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#define MBI_MCR_OFFSET 0xD0
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#define MBI_MDR_OFFSET 0xD4
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#define MBI_MCRX_OFFSET 0xD8
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#define MBI_RD_MASK 0xFEFFFFFF
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#define MBI_WR_MASK 0X01000000
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#define MBI_MASK_HI 0xFFFFFF00
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#define MBI_MASK_LO 0x000000FF
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#define MBI_ENABLE 0xF0
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/* IOSF SB read/write opcodes */
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#define MBI_MMIO_READ 0x00
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#define MBI_MMIO_WRITE 0x01
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#define MBI_CFG_READ 0x04
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#define MBI_CFG_WRITE 0x05
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#define MBI_CR_READ 0x06
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#define MBI_CR_WRITE 0x07
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#define MBI_REG_READ 0x10
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#define MBI_REG_WRITE 0x11
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#define MBI_ESRAM_READ 0x12
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#define MBI_ESRAM_WRITE 0x13
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/* Baytrail available units */
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#define BT_MBI_UNIT_AUNIT 0x00
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#define BT_MBI_UNIT_SMC 0x01
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#define BT_MBI_UNIT_CPU 0x02
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#define BT_MBI_UNIT_BUNIT 0x03
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#define BT_MBI_UNIT_PMC 0x04
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#define BT_MBI_UNIT_GFX 0x06
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#define BT_MBI_UNIT_SMI 0x0C
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#define BT_MBI_UNIT_USB 0x43
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#define BT_MBI_UNIT_SATA 0xA3
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#define BT_MBI_UNIT_PCIE 0xA6
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/* Quark available units */
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#define QRK_MBI_UNIT_HBA 0x00
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#define QRK_MBI_UNIT_HB 0x03
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#define QRK_MBI_UNIT_RMU 0x04
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#define QRK_MBI_UNIT_MM 0x05
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#define QRK_MBI_UNIT_SOC 0x31
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#if IS_ENABLED(CONFIG_IOSF_MBI)
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bool iosf_mbi_available(void);
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/**
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* iosf_mbi_read() - MailBox Interface read command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data to be read
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr);
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/**
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* iosf_mbi_write() - MailBox unmasked write command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data to be written
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr);
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/**
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* iosf_mbi_modify() - MailBox masked write command
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* @port: port indicating subunit being accessed
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* @opcode: port specific read or write opcode
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* @offset: register address offset
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* @mdr: register data being modified
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* @mask: mask indicating bits in mdr to be modified
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*
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* Locking is handled by spinlock - cannot sleep.
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* Return: Nonzero on error
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*/
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int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask);
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#else /* CONFIG_IOSF_MBI is not enabled */
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static inline
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bool iosf_mbi_available(void)
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{
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return false;
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}
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static inline
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int iosf_mbi_read(u8 port, u8 opcode, u32 offset, u32 *mdr)
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{
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WARN(1, "IOSF_MBI driver not available");
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return -EPERM;
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}
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static inline
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int iosf_mbi_write(u8 port, u8 opcode, u32 offset, u32 mdr)
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{
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WARN(1, "IOSF_MBI driver not available");
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return -EPERM;
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}
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static inline
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int iosf_mbi_modify(u8 port, u8 opcode, u32 offset, u32 mdr, u32 mask)
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{
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WARN(1, "IOSF_MBI driver not available");
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return -EPERM;
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}
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#endif /* CONFIG_IOSF_MBI */
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#endif /* IOSF_MBI_SYMS_H */
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