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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b6138ed604
This patch fixes a potential hole when configuring the cycle counter used to generate the nanosecond time clock. This clock is based off of the SYSTIME registers along with the TIMINCA registers. The TIMINCA register determines the increment to be added to the SYSTIME registers every DMA clock tick. This register needs to be reconfigured whenever the link-speed changes. However, the value calculated stays the same when link is down and when link is up. Misconfiguration can occur if the link status changes due to a reset, which causes the TIMINCA register to be reset. This reset puts the device in an unstable state where the SYSTIME registers stop incrementing and the PTP protocol does not function. The solution is to double check the TIMINCA value and always reset the value if the register is zero. This prevents a misconfiguration bug that halts the PHC. Signed-off-by: Jacob Keller <jacob.e.keller@intel.com> Acked-by: Don Skidmore <donald.c.skidmore@intel.com> Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com> Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com> Signed-off-by: David S. Miller <davem@davemloft.net> |
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| .. | ||
| ixgbe_82598.c | ||
| ixgbe_82599.c | ||
| ixgbe_common.c | ||
| ixgbe_common.h | ||
| ixgbe_dcb_82598.c | ||
| ixgbe_dcb_82598.h | ||
| ixgbe_dcb_82599.c | ||
| ixgbe_dcb_82599.h | ||
| ixgbe_dcb_nl.c | ||
| ixgbe_dcb.c | ||
| ixgbe_dcb.h | ||
| ixgbe_ethtool.c | ||
| ixgbe_fcoe.c | ||
| ixgbe_fcoe.h | ||
| ixgbe_lib.c | ||
| ixgbe_main.c | ||
| ixgbe_mbx.c | ||
| ixgbe_mbx.h | ||
| ixgbe_phy.c | ||
| ixgbe_phy.h | ||
| ixgbe_ptp.c | ||
| ixgbe_sriov.c | ||
| ixgbe_sriov.h | ||
| ixgbe_sysfs.c | ||
| ixgbe_type.h | ||
| ixgbe_x540.c | ||
| ixgbe.h | ||
| Makefile | ||