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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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7c607944bc
The CNTVOFF register from arch timer is uninitialized. It should be done by the bootloader but it is currently not the case, even for boot CPU because this SoC is booting in secure mode. It leads to an random offset value meaning that each CPU will have a different time, which isn't working very well. Add assembly code used for boot CPU and secondary CPU cores to make sure that the CNTVOFF register is initialized. Because this code can be used by different platforms, add this assembly file in ARM's common folder. Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Tested-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
21 lines
656 B
Makefile
21 lines
656 B
Makefile
# SPDX-License-Identifier: GPL-2.0
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#
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# Makefile for the linux kernel.
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#
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obj-y += firmware.o
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obj-$(CONFIG_SA1111) += sa1111.o
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obj-$(CONFIG_DMABOUNCE) += dmabounce.o
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obj-$(CONFIG_SHARP_LOCOMO) += locomo.o
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obj-$(CONFIG_SHARP_PARAM) += sharpsl_param.o
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obj-$(CONFIG_SHARP_SCOOP) += scoop.o
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obj-$(CONFIG_SMP) += secure_cntvoff.o
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obj-$(CONFIG_PCI_HOST_ITE8152) += it8152.o
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obj-$(CONFIG_MCPM) += mcpm_head.o mcpm_entry.o mcpm_platsmp.o vlock.o
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CFLAGS_REMOVE_mcpm_entry.o = -pg
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AFLAGS_mcpm_head.o := -march=armv7-a
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AFLAGS_vlock.o := -march=armv7-a
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obj-$(CONFIG_BL_SWITCHER) += bL_switcher.o
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obj-$(CONFIG_BL_SWITCHER_DUMMY_IF) += bL_switcher_dummy_if.o
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