mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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a26be149fa
This time with:
* Generic page-table framework for ARM IOMMUs using the LPAE page-table
format, ARM-SMMU and Renesas IPMMU make use of it already.
* Break out of the IO virtual address allocator from the Intel IOMMU so
that it can be used by other DMA-API implementations too. The first
user will be the ARM64 common DMA-API implementation for IOMMUs
* Device tree support for Renesas IPMMU
* Various fixes and cleanups all over the place
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Merge tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull IOMMU updates from Joerg Roedel:
"This time with:
- Generic page-table framework for ARM IOMMUs using the LPAE
page-table format, ARM-SMMU and Renesas IPMMU make use of it
already.
- Break out the IO virtual address allocator from the Intel IOMMU so
that it can be used by other DMA-API implementations too. The
first user will be the ARM64 common DMA-API implementation for
IOMMUs
- Device tree support for Renesas IPMMU
- Various fixes and cleanups all over the place"
* tag 'iommu-updates-v3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (36 commits)
iommu/amd: Convert non-returned local variable to boolean when relevant
iommu: Update my email address
iommu/amd: Use wait_event in put_pasid_state_wait
iommu/amd: Fix amd_iommu_free_device()
iommu/arm-smmu: Avoid build warning
iommu/fsl: Various cleanups
iommu/fsl: Use %pa to print phys_addr_t
iommu/omap: Print phys_addr_t using %pa
iommu: Make more drivers depend on COMPILE_TEST
iommu/ipmmu-vmsa: Fix IOMMU lookup when multiple IOMMUs are registered
iommu: Disable on !MMU builds
iommu/fsl: Remove unused fsl_of_pamu_ids[]
iommu/fsl: Fix section mismatch
iommu/ipmmu-vmsa: Use the ARM LPAE page table allocator
iommu: Fix trace_map() to report original iova and original size
iommu/arm-smmu: add support for iova_to_phys through ATS1PR
iopoll: Introduce memory-mapped IO polling macros
iommu/arm-smmu: don't touch the secure STLBIALL register
iommu/arm-smmu: make use of generic LPAE allocator
iommu: io-pgtable-arm: add non-secure quirk
...
93 lines
3.3 KiB
C
93 lines
3.3 KiB
C
/*
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* Copyright (C) 2009-2010 Advanced Micro Devices, Inc.
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* Author: Joerg Roedel <jroedel@suse.de>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ASM_X86_AMD_IOMMU_PROTO_H
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#define _ASM_X86_AMD_IOMMU_PROTO_H
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#include "amd_iommu_types.h"
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extern int amd_iommu_init_dma_ops(void);
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extern int amd_iommu_init_passthrough(void);
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extern irqreturn_t amd_iommu_int_thread(int irq, void *data);
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extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
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extern void amd_iommu_apply_erratum_63(u16 devid);
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extern void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu);
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extern int amd_iommu_init_devices(void);
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extern void amd_iommu_uninit_devices(void);
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extern void amd_iommu_init_notifier(void);
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extern void amd_iommu_init_api(void);
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/* Needed for interrupt remapping */
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extern int amd_iommu_prepare(void);
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extern int amd_iommu_enable(void);
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extern void amd_iommu_disable(void);
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extern int amd_iommu_reenable(int);
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extern int amd_iommu_enable_faulting(void);
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/* IOMMUv2 specific functions */
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struct iommu_domain;
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extern bool amd_iommu_v2_supported(void);
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extern int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
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extern int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
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extern void amd_iommu_domain_direct_map(struct iommu_domain *dom);
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extern int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids);
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extern int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
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u64 address);
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extern int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid);
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extern int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
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unsigned long cr3);
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extern int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid);
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extern struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev);
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/* IOMMU Performance Counter functions */
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extern bool amd_iommu_pc_supported(void);
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extern u8 amd_iommu_pc_get_max_banks(u16 devid);
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extern u8 amd_iommu_pc_get_max_counters(u16 devid);
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extern int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
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u64 *value, bool is_write);
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#define PPR_SUCCESS 0x0
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#define PPR_INVALID 0x1
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#define PPR_FAILURE 0xf
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extern int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
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int status, int tag);
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#ifndef CONFIG_AMD_IOMMU_STATS
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static inline void amd_iommu_stats_init(void) { }
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#endif /* !CONFIG_AMD_IOMMU_STATS */
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static inline bool is_rd890_iommu(struct pci_dev *pdev)
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{
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return (pdev->vendor == PCI_VENDOR_ID_ATI) &&
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(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
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}
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static inline bool iommu_feature(struct amd_iommu *iommu, u64 f)
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{
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if (!(iommu->cap & (1 << IOMMU_CAP_EFR)))
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return false;
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return !!(iommu->features & f);
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}
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#endif /* _ASM_X86_AMD_IOMMU_PROTO_H */
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