mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2025-03-04 06:29:17 +07:00
![]() The highbank clock will glitch with the current code if the clock rate is reset without relocking the PLL. Program the PLL correctly to prevent glitches. Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com> Signed-off-by: Rob Herring <rob.herring@calxeda.com> Acked-by: Mike Turquette <mturquette@linaro.org> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> |
||
---|---|---|
.. | ||
mmp | ||
mvebu | ||
mxs | ||
socfpga | ||
spear | ||
ux500 | ||
versatile | ||
clk-bcm2835.c | ||
clk-devres.c | ||
clk-divider.c | ||
clk-fixed-factor.c | ||
clk-fixed-rate.c | ||
clk-gate.c | ||
clk-highbank.c | ||
clk-ls1x.c | ||
clk-max77686.c | ||
clk-mux.c | ||
clk-nomadik.c | ||
clk-prima2.c | ||
clk-sunxi.c | ||
clk-twl6040.c | ||
clk-u300.c | ||
clk-vt8500.c | ||
clk-wm831x.c | ||
clk-zynq.c | ||
clk.c | ||
clkdev.c | ||
Kconfig | ||
Makefile |