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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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263 lines
7.1 KiB
C
263 lines
7.1 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2005 Embedded Alley Solutions, Inc
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*/
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#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
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#define __ASM_MACH_KERNEL_ENTRY_INIT_H
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#include <asm/cacheops.h>
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#include <asm/addrspace.h>
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#define CO_CONFIGPR_VALID 0x3F1F41FF /* valid bits to write to ConfigPR */
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#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
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#define CACHE_OPC 0xBC000000 /* MIPS cache instruction opcode */
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#define ICACHE_LINE_SIZE 32 /* Instruction cache line size bytes */
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#define DCACHE_LINE_SIZE 32 /* Data cache line size in bytes */
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#define ICACHE_SET_COUNT 256 /* Instruction cache set count */
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#define DCACHE_SET_COUNT 128 /* Data cache set count */
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#define ICACHE_SET_SIZE (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
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#define DCACHE_SET_SIZE (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
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.macro kernel_entry_setup
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.set push
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.set noreorder
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/*
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* PNX8550 entry point, when running a non compressed
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* kernel. When loading a zImage, the head.S code in
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* arch/mips/zboot/pnx8550 will init the caches and,
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* decompress the kernel, and branch to kernel_entry.
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*/
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cache_begin: li t0, (1<<28)
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mtc0 t0, CP0_STATUS /* cp0 usable */
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HAZARD_CP0
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mtc0 zero, CP0_CAUSE
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HAZARD_CP0
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/* Set static virtual to phys address translation and TLB disabled */
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mfc0 t0, CP0_CONFIG, 7
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HAZARD_CP0
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and t0, ~((1<<19) | (1<<20)) /* TLB/MAP cleared */
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mtc0 t0, CP0_CONFIG, 7
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HAZARD_CP0
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/* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
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init_icache
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nop
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init_dcache
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nop
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cachePr4450ICReset
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nop
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cachePr4450DCReset
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nop
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/* read ConfigPR into t0 */
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mfc0 t0, CP0_CONFIG, 7
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HAZARD_CP0
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/* enable the TLB */
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or t0, (1<<19)
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/* disable the ICACHE: at least 10x slower */
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/* or t0, (1<<26) */
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/* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set */
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/* or t0, (1<<27) */
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and t0, CO_CONFIGPR_VALID
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/* enable TLB. */
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mtc0 t0, CP0_CONFIG, 7
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HAZARD_CP0
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cache_end:
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/* Setup CMEM_0 to MMIO address space, 2MB */
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lui t0, 0x1BE0
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addi t0, t0, 0x3
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mtc0 $8, $22, 4
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nop
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/* Setup CMEM_1, 128MB */
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lui t0, 0x1000
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addi t0, t0, 0xf
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mtc0 $8, $22, 5
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nop
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/* Setup CMEM_2, 32MB */
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lui t0, 0x1C00
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addi t0, t0, 0xb
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mtc0 $8, $22, 6
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nop
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/* Setup CMEM_3, 0MB */
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lui t0, 0x0
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addi t0, t0, 0x0
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mtc0 $8, $22, 7
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nop
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/* Enable cache */
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mfc0 t0, CP0_CONFIG
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HAZARD_CP0
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and t0, t0, 0xFFFFFFF8
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or t0, t0, 3
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mtc0 t0, CP0_CONFIG
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HAZARD_CP0
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.set pop
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.endm
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.macro init_icache
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.set push
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.set noreorder
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/* Get Cache Configuration */
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mfc0 t3, CP0_CONFIG, 1
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HAZARD_CP0
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/* get cache Line size */
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srl t1, t3, 19 /* C0_CONFIGPR_IL_SHIFT */
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andi t1, t1, 0x7 /* C0_CONFIGPR_IL_MASK */
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beq t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
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nop
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addiu t0, t1, 1
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ori t1, zero, 1
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sllv t1, t1, t0
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/* get max cache Index */
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srl t2, t3, 22 /* C0_CONFIGPR_IS_SHIFT */
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andi t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
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addiu t0, t2, 6
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ori t2, zero, 1
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sllv t2, t2, t0
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/* get max cache way */
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srl t3, t3, 16 /* C0_CONFIGPR_IA_SHIFT */
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andi t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
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addiu t3, t3, 1
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/* total no of cache lines */
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multu t2, t3 /* max index * max way */
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mflo t2
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addiu t2, t2, -1
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move t0, zero
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pr4450_next_instruction_cache_set:
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cache Index_Invalidate_I, 0(t0)
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addu t0, t0, t1 /* add bytes in a line */
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bne t2, zero, pr4450_next_instruction_cache_set
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addiu t2, t2, -1 /* reduce no of lines to invalidate by one */
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pr4450_instr_cache_invalidated:
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.set pop
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.endm
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.macro init_dcache
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.set push
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.set noreorder
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move t1, zero
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/* Store Tag Information */
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mtc0 zero, CP0_TAGLO, 0
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HAZARD_CP0
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mtc0 zero, CP0_TAGHI, 0
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HAZARD_CP0
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/* Cache size is 16384 = 512 lines x 32 bytes per line */
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or t2, zero, (128*4)-1 /* 512 lines */
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/* Invalidate all lines */
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2:
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cache Index_Store_Tag_D, 0(t1)
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addiu t2, t2, -1
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bne t2, zero, 2b
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addiu t1, t1, 32 /* 32 bytes in a line */
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.set pop
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.endm
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.macro cachePr4450ICReset
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.set push
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.set noreorder
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/* Save CP0 status reg on entry; */
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/* disable interrupts during cache reset */
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mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
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HAZARD_CP0
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mtc0 zero, CP0_STATUS /* disable CPU interrupts */
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HAZARD_CP0
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or t1, zero, zero /* T1 = starting cache index (0) */
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ori t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
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icache_invd_loop:
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/* 9 == register t1 */
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.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
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(0 * ICACHE_SET_SIZE) /* invalidate inst cache WAY0 */
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.word CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
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(1 * ICACHE_SET_SIZE) /* invalidate inst cache WAY1 */
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addiu t1, t1, ICACHE_LINE_SIZE /* T1 = next cache line index */
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bne t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
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addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
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/* Initialize the latches in the instruction cache tag */
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/* that drive the way selection tri-state bus drivers, by doing a */
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/* dummy load while the instruction cache is still disabled. */
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/* TODO: Is this needed ? */
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la t1, KSEG0 /* T1 = cached memory base address */
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lw zero, 0x0000(t1) /* (dummy read of first memory word) */
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mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
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HAZARD_CP0
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.set pop
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.endm
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.macro cachePr4450DCReset
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.set push
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.set noreorder
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mfc0 t0, CP0_STATUS /* T0 = interrupt status on entry */
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HAZARD_CP0
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mtc0 zero, CP0_STATUS /* disable CPU interrupts */
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HAZARD_CP0
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/* Writeback/invalidate entire data cache sets/ways/lines */
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or t1, zero, zero /* T1 = starting cache index (0) */
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ori t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
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dcache_wbinvd_loop:
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/* 9 == register t1 */
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.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
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(0 * DCACHE_SET_SIZE) /* writeback/invalidate WAY0 */
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.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
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(1 * DCACHE_SET_SIZE) /* writeback/invalidate WAY1 */
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.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
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(2 * DCACHE_SET_SIZE) /* writeback/invalidate WAY2 */
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.word CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
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(3 * DCACHE_SET_SIZE) /* writeback/invalidate WAY3 */
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addiu t1, t1, DCACHE_LINE_SIZE /* T1 = next data cache line index */
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bne t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
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addiu t2, t2, -1 /* decrement T2 set cnt (delay slot) */
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/* Initialize the latches in the data cache tag that drive the way
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selection tri-state bus drivers, by doing a dummy load while the
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data cache is still in the disabled mode. TODO: Is this needed ? */
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la t1, KSEG0 /* T1 = cached memory base address */
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lw zero, 0x0000(t1) /* (dummy read of first memory word) */
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mtc0 t0, CP0_STATUS /* restore interrupt status on entry */
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HAZARD_CP0
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.set pop
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.endm
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#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
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