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![]() KVM has special logic to handle pages with pte.u=1 and pte.w=0 when
CR0.WP=1. These pages' SPTEs flip continuously between two states:
U=1/W=0 (user and supervisor reads allowed, supervisor writes not allowed)
and U=0/W=1 (supervisor reads and writes allowed, user writes not allowed).
When SMEP is in effect, however, U=0 will enable kernel execution of
this page. To avoid this, KVM also sets NX=1 in the shadow PTE together
with U=0, making the two states U=1/W=0/NX=gpte.NX and U=0/W=1/NX=1.
When guest EFER has the NX bit cleared, the reserved bit check thinks
that the latter state is invalid; teach it that the smep_andnot_wp case
will also use the NX bit of SPTEs.
Cc: stable@vger.kernel.org
Reviewed-by: Xiao Guangrong <guangrong.xiao@linux.inel.com>
Fixes:
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.. | ||
assigned-dev.c | ||
assigned-dev.h | ||
cpuid.c | ||
cpuid.h | ||
emulate.c | ||
hyperv.c | ||
hyperv.h | ||
i8254.c | ||
i8254.h | ||
i8259.c | ||
ioapic.c | ||
ioapic.h | ||
iommu.c | ||
irq_comm.c | ||
irq.c | ||
irq.h | ||
Kconfig | ||
kvm_cache_regs.h | ||
lapic.c | ||
lapic.h | ||
Makefile | ||
mmu_audit.c | ||
mmu.c | ||
mmu.h | ||
mmutrace.h | ||
mtrr.c | ||
paging_tmpl.h | ||
pmu_amd.c | ||
pmu_intel.c | ||
pmu.c | ||
pmu.h | ||
svm.c | ||
trace.h | ||
tss.h | ||
vmx.c | ||
x86.c | ||
x86.h |