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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e82cb03f5a
The simulataneous transmission of both WLAN and BT might cause increase in power levels. To avoid regulatory violation, WLAN tx power will be adjusted according to BT power index based on avaliability of BT scheduling messages. WLAN tx power reduction might affect its performance. So WLAN tx power is only be lowered when the signal strength is good enough. Otherwise concurrent tx will be disabled and WLAN uses it default power levels. Also concurrent tx is disabled whenever WLAN is moving to off-channel which might be used by BT. Signed-off-by: Rajkumar Manoharan <rmanohar@qca.qualcomm.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
177 lines
4.8 KiB
C
177 lines
4.8 KiB
C
/*
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* Copyright (c) 2010-2011 Atheros Communications Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#ifndef MCI_H
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#define MCI_H
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#include "ar9003_mci.h"
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#define ATH_MCI_SCHED_BUF_SIZE (16 * 16) /* 16 entries, 4 dword each */
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#define ATH_MCI_GPM_MAX_ENTRY 16
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#define ATH_MCI_GPM_BUF_SIZE (ATH_MCI_GPM_MAX_ENTRY * 16)
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#define ATH_MCI_DEF_BT_PERIOD 40
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#define ATH_MCI_BDR_DUTY_CYCLE 20
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#define ATH_MCI_MAX_DUTY_CYCLE 90
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#define ATH_MCI_DEF_AGGR_LIMIT 6 /* in 0.24 ms */
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#define ATH_MCI_MAX_ACL_PROFILE 7
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#define ATH_MCI_MAX_SCO_PROFILE 1
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#define ATH_MCI_MAX_PROFILE (ATH_MCI_MAX_ACL_PROFILE +\
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ATH_MCI_MAX_SCO_PROFILE)
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#define ATH_MCI_INQUIRY_PRIO 62
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#define ATH_MCI_HI_PRIO 60
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#define ATH_MCI_NUM_BT_CHANNELS 79
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#define ATH_MCI_CONCUR_TX_SWITCH 5
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#define MCI_GPM_SET_CHANNEL_BIT(_p_gpm, _bt_chan) \
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do { \
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if (_bt_chan < ATH_MCI_NUM_BT_CHANNELS) { \
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*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
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(_bt_chan / 8)) |= (1 << (_bt_chan & 7)); \
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} \
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} while (0)
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#define MCI_GPM_CLR_CHANNEL_BIT(_p_gpm, _bt_chan) \
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do { \
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if (_bt_chan < ATH_MCI_NUM_BT_CHANNELS) { \
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*(((u8 *)(_p_gpm)) + MCI_GPM_COEX_B_CHANNEL_MAP + \
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(_bt_chan / 8)) &= ~(1 << (_bt_chan & 7));\
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} \
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} while (0)
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#define INC_PROF(_mci, _info) do { \
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switch (_info->type) { \
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case MCI_GPM_COEX_PROFILE_RFCOMM:\
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_mci->num_other_acl++; \
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break; \
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case MCI_GPM_COEX_PROFILE_A2DP: \
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_mci->num_a2dp++; \
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if (!_info->edr) \
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_mci->num_bdr++; \
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break; \
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case MCI_GPM_COEX_PROFILE_HID: \
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_mci->num_hid++; \
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break; \
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case MCI_GPM_COEX_PROFILE_BNEP: \
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_mci->num_pan++; \
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break; \
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case MCI_GPM_COEX_PROFILE_VOICE: \
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_mci->num_sco++; \
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break; \
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default: \
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break; \
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} \
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} while (0)
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#define DEC_PROF(_mci, _info) do { \
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switch (_info->type) { \
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case MCI_GPM_COEX_PROFILE_RFCOMM:\
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_mci->num_other_acl--; \
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break; \
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case MCI_GPM_COEX_PROFILE_A2DP: \
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_mci->num_a2dp--; \
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if (!_info->edr) \
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_mci->num_bdr--; \
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break; \
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case MCI_GPM_COEX_PROFILE_HID: \
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_mci->num_hid--; \
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break; \
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case MCI_GPM_COEX_PROFILE_BNEP: \
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_mci->num_pan--; \
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break; \
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case MCI_GPM_COEX_PROFILE_VOICE: \
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_mci->num_sco--; \
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break; \
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default: \
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break; \
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} \
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} while (0)
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#define NUM_PROF(_mci) (_mci->num_other_acl + _mci->num_a2dp + \
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_mci->num_hid + _mci->num_pan + _mci->num_sco)
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struct ath_mci_profile_info {
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u8 type;
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u8 conn_handle;
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bool start;
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bool master;
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bool edr;
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u8 voice_type;
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u16 T; /* Voice: Tvoice, HID: Tsniff, in slots */
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u8 W; /* Voice: Wvoice, HID: Sniff timeout, in slots */
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u8 A; /* HID: Sniff attempt, in slots */
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struct list_head list;
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};
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struct ath_mci_profile_status {
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bool is_critical;
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bool is_link;
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u8 conn_handle;
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};
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struct ath_mci_profile {
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struct list_head info;
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DECLARE_BITMAP(status, ATH_MCI_MAX_PROFILE);
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u16 aggr_limit;
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u8 num_mgmt;
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u8 num_sco;
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u8 num_a2dp;
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u8 num_hid;
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u8 num_pan;
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u8 num_other_acl;
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u8 num_bdr;
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u8 voice_priority;
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};
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struct ath_mci_buf {
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void *bf_addr; /* virtual addr of desc */
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dma_addr_t bf_paddr; /* physical addr of buffer */
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u32 bf_len; /* len of data */
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};
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struct ath_mci_coex {
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struct ath_mci_buf sched_buf;
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struct ath_mci_buf gpm_buf;
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};
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void ath_mci_flush_profile(struct ath_mci_profile *mci);
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int ath_mci_setup(struct ath_softc *sc);
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void ath_mci_cleanup(struct ath_softc *sc);
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void ath_mci_intr(struct ath_softc *sc);
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void ath9k_mci_update_rssi(struct ath_softc *sc);
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#ifdef CONFIG_ATH9K_BTCOEX_SUPPORT
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void ath_mci_enable(struct ath_softc *sc);
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void ath9k_mci_update_wlan_channels(struct ath_softc *sc, bool allow_all);
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void ath9k_mci_set_txpower(struct ath_softc *sc, bool setchannel,
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bool concur_tx);
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#else
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static inline void ath_mci_enable(struct ath_softc *sc)
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{
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}
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static inline void ath9k_mci_update_wlan_channels(struct ath_softc *sc,
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bool allow_all)
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{
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}
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static inline void ath9k_mci_set_txpower(struct ath_softc *sc, bool setchannel,
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bool concur_tx)
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{
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}
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#endif /* CONFIG_ATH9K_BTCOEX_SUPPORT */
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#endif /* MCI_H*/
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