mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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13da9e200f
This reverts commitb3b77c8cae, which was also totally broken (see commit0d2daf5cc8that reverted the crc32 version of it). As reported by Stephen Rothwell, it causes problems on big-endian machines: > In file included from fs/jfs/jfs_types.h:33, > from fs/jfs/jfs_incore.h:26, > from fs/jfs/file.c:22: > fs/jfs/endian24.h:36:101: warning: "__LITTLE_ENDIAN" is not defined The kernel has never had that crazy "__BYTE_ORDER == __LITTLE_ENDIAN" model. It's not how we do things, and it isn't how we _should_ do things. So don't go there. Requested-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
378 lines
13 KiB
C
378 lines
13 KiB
C
/* Machine-dependent software floating-point definitions. PPC version.
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Copyright (C) 1997 Free Software Foundation, Inc.
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This file is part of the GNU C Library.
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The GNU C Library is free software; you can redistribute it and/or
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modify it under the terms of the GNU Library General Public License as
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published by the Free Software Foundation; either version 2 of the
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License, or (at your option) any later version.
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The GNU C Library is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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Library General Public License for more details.
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You should have received a copy of the GNU Library General Public
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License along with the GNU C Library; see the file COPYING.LIB. If
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not, write to the Free Software Foundation, Inc.,
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59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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Actually, this is a PPC (32bit) version, written based on the
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i386, sparc, and sparc64 versions, by me,
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Peter Maydell (pmaydell@chiark.greenend.org.uk).
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Comments are by and large also mine, although they may be inaccurate.
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In picking out asm fragments I've gone with the lowest common
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denominator, which also happens to be the hardware I have :->
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That is, a SPARC without hardware multiply and divide.
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*/
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/* basic word size definitions */
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#define _FP_W_TYPE_SIZE 32
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#define _FP_W_TYPE unsigned int
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#define _FP_WS_TYPE signed int
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#define _FP_I_TYPE int
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#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
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#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
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#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
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/* You can optionally code some things like addition in asm. For
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* example, i386 defines __FP_FRAC_ADD_2 as asm. If you don't
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* then you get a fragment of C code [if you change an #ifdef 0
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* in op-2.h] or a call to add_ssaaaa (see below).
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* Good places to look for asm fragments to use are gcc and glibc.
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* gcc's longlong.h is useful.
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*/
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/* We need to know how to multiply and divide. If the host word size
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* is >= 2*fracbits you can use FP_MUL_MEAT_n_imm(t,R,X,Y) which
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* codes the multiply with whatever gcc does to 'a * b'.
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* _FP_MUL_MEAT_n_wide(t,R,X,Y,f) is used when you have an asm
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* function that can multiply two 1W values and get a 2W result.
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* Otherwise you're stuck with _FP_MUL_MEAT_n_hard(t,R,X,Y) which
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* does bitshifting to avoid overflow.
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* For division there is FP_DIV_MEAT_n_imm(t,R,X,Y,f) for word size
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* >= 2*fracbits, where f is either _FP_DIV_HELP_imm or
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* _FP_DIV_HELP_ldiv (see op-1.h).
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* _FP_DIV_MEAT_udiv() is if you have asm to do 2W/1W => (1W, 1W).
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* [GCC and glibc have longlong.h which has the asm macro udiv_qrnnd
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* to do this.]
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* In general, 'n' is the number of words required to hold the type,
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* and 't' is either S, D or Q for single/double/quad.
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* -- PMM
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*/
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/* Example: SPARC64:
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* #define _FP_MUL_MEAT_S(R,X,Y) _FP_MUL_MEAT_1_imm(S,R,X,Y)
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* #define _FP_MUL_MEAT_D(R,X,Y) _FP_MUL_MEAT_1_wide(D,R,X,Y,umul_ppmm)
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* #define _FP_MUL_MEAT_Q(R,X,Y) _FP_MUL_MEAT_2_wide(Q,R,X,Y,umul_ppmm)
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*
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* #define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_imm(S,R,X,Y,_FP_DIV_HELP_imm)
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* #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_1_udiv(D,R,X,Y)
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* #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_2_udiv_64(Q,R,X,Y)
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*
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* Example: i386:
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* #define _FP_MUL_MEAT_S(R,X,Y) _FP_MUL_MEAT_1_wide(S,R,X,Y,_i386_mul_32_64)
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* #define _FP_MUL_MEAT_D(R,X,Y) _FP_MUL_MEAT_2_wide(D,R,X,Y,_i386_mul_32_64)
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*
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* #define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv(S,R,X,Y,_i386_div_64_32)
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* #define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv_64(D,R,X,Y)
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*/
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#define _FP_MUL_MEAT_S(R,X,Y) _FP_MUL_MEAT_1_wide(_FP_WFRACBITS_S,R,X,Y,umul_ppmm)
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#define _FP_MUL_MEAT_D(R,X,Y) _FP_MUL_MEAT_2_wide(_FP_WFRACBITS_D,R,X,Y,umul_ppmm)
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#define _FP_DIV_MEAT_S(R,X,Y) _FP_DIV_MEAT_1_udiv_norm(S,R,X,Y)
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#define _FP_DIV_MEAT_D(R,X,Y) _FP_DIV_MEAT_2_udiv(D,R,X,Y)
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/* These macros define what NaN looks like. They're supposed to expand to
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* a comma-separated set of 32bit unsigned ints that encode NaN.
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*/
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#define _FP_NANFRAC_S ((_FP_QNANBIT_S << 1) - 1)
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#define _FP_NANFRAC_D ((_FP_QNANBIT_D << 1) - 1), -1
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#define _FP_NANFRAC_Q ((_FP_QNANBIT_Q << 1) - 1), -1, -1, -1
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#define _FP_NANSIGN_S 0
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#define _FP_NANSIGN_D 0
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#define _FP_NANSIGN_Q 0
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#define _FP_KEEPNANFRACP 1
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#ifdef FP_EX_BOOKE_E500_SPE
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#define FP_EX_INEXACT (1 << 21)
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#define FP_EX_INVALID (1 << 20)
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#define FP_EX_DIVZERO (1 << 19)
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#define FP_EX_UNDERFLOW (1 << 18)
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#define FP_EX_OVERFLOW (1 << 17)
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#define FP_INHIBIT_RESULTS 0
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#define __FPU_FPSCR (current->thread.spefscr)
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#define __FPU_ENABLED_EXC \
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({ \
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(__FPU_FPSCR >> 2) & 0x1f; \
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})
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#else
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/* Exception flags. We use the bit positions of the appropriate bits
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in the FPSCR, which also correspond to the FE_* bits. This makes
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everything easier ;-). */
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#define FP_EX_INVALID (1 << (31 - 2))
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#define FP_EX_INVALID_SNAN EFLAG_VXSNAN
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#define FP_EX_INVALID_ISI EFLAG_VXISI
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#define FP_EX_INVALID_IDI EFLAG_VXIDI
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#define FP_EX_INVALID_ZDZ EFLAG_VXZDZ
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#define FP_EX_INVALID_IMZ EFLAG_VXIMZ
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#define FP_EX_OVERFLOW (1 << (31 - 3))
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#define FP_EX_UNDERFLOW (1 << (31 - 4))
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#define FP_EX_DIVZERO (1 << (31 - 5))
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#define FP_EX_INEXACT (1 << (31 - 6))
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#define __FPU_FPSCR (current->thread.fpscr.val)
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/* We only actually write to the destination register
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* if exceptions signalled (if any) will not trap.
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*/
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#define __FPU_ENABLED_EXC \
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({ \
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(__FPU_FPSCR >> 3) & 0x1f; \
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})
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#endif
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/*
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* If one NaN is signaling and the other is not,
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* we choose that one, otherwise we choose X.
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*/
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#define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
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do { \
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if ((_FP_FRAC_HIGH_RAW_##fs(Y) & _FP_QNANBIT_##fs) \
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&& !(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs)) \
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{ \
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R##_s = X##_s; \
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_FP_FRAC_COPY_##wc(R,X); \
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} \
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else \
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{ \
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R##_s = Y##_s; \
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_FP_FRAC_COPY_##wc(R,Y); \
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} \
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R##_c = FP_CLS_NAN; \
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} while (0)
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#define __FPU_TRAP_P(bits) \
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((__FPU_ENABLED_EXC & (bits)) != 0)
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#define __FP_PACK_S(val,X) \
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({ int __exc = _FP_PACK_CANONICAL(S,1,X); \
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if(!__exc || !__FPU_TRAP_P(__exc)) \
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_FP_PACK_RAW_1_P(S,val,X); \
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__exc; \
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})
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#define __FP_PACK_D(val,X) \
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do { \
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_FP_PACK_CANONICAL(D, 2, X); \
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if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS)) \
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_FP_PACK_RAW_2_P(D, val, X); \
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} while (0)
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#define __FP_PACK_DS(val,X) \
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do { \
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FP_DECL_S(__X); \
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FP_CONV(S, D, 1, 2, __X, X); \
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_FP_PACK_CANONICAL(S, 1, __X); \
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if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS)) { \
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_FP_UNPACK_CANONICAL(S, 1, __X); \
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FP_CONV(D, S, 2, 1, X, __X); \
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_FP_PACK_CANONICAL(D, 2, X); \
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if (!FP_CUR_EXCEPTIONS || !__FPU_TRAP_P(FP_CUR_EXCEPTIONS)) \
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_FP_PACK_RAW_2_P(D, val, X); \
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} \
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} while (0)
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/* Obtain the current rounding mode. */
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#define FP_ROUNDMODE \
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({ \
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__FPU_FPSCR & 0x3; \
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})
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/* the asm fragments go here: all these are taken from glibc-2.0.5's
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* stdlib/longlong.h
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*/
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#include <linux/types.h>
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#include <asm/byteorder.h>
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/* add_ssaaaa is used in op-2.h and should be equivalent to
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* #define add_ssaaaa(sh,sl,ah,al,bh,bl) (sh = ah+bh+ (( sl = al+bl) < al))
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* add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
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* high_addend_2, low_addend_2) adds two UWtype integers, composed by
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* HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
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* respectively. The result is placed in HIGH_SUM and LOW_SUM. Overflow
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* (i.e. carry out) is not stored anywhere, and is lost.
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*/
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#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
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do { \
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if (__builtin_constant_p (bh) && (bh) == 0) \
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__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl))); \
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else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
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__asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl))); \
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else \
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__asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "%r" ((USItype)(ah)), \
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"r" ((USItype)(bh)), \
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"%r" ((USItype)(al)), \
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"rI" ((USItype)(bl))); \
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} while (0)
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/* sub_ddmmss is used in op-2.h and udivmodti4.c and should be equivalent to
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* #define sub_ddmmss(sh, sl, ah, al, bh, bl) (sh = ah-bh - ((sl = al-bl) > al))
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* sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
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* high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
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* composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
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* LOW_SUBTRAHEND_2 respectively. The result is placed in HIGH_DIFFERENCE
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* and LOW_DIFFERENCE. Overflow (i.e. carry out) is not stored anywhere,
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* and is lost.
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*/
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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do { \
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if (__builtin_constant_p (ah) && (ah) == 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(bh)), \
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"rI" ((USItype)(al)), \
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"r" ((USItype)(bl))); \
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else if (__builtin_constant_p (ah) && (ah) ==~(USItype) 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(bh)), \
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"rI" ((USItype)(al)), \
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"r" ((USItype)(bl))); \
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else if (__builtin_constant_p (bh) && (bh) == 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(ah)), \
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"rI" ((USItype)(al)), \
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"r" ((USItype)(bl))); \
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else if (__builtin_constant_p (bh) && (bh) ==~(USItype) 0) \
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__asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(ah)), \
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"rI" ((USItype)(al)), \
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"r" ((USItype)(bl))); \
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else \
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__asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2" \
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: "=r" ((USItype)(sh)), \
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"=&r" ((USItype)(sl)) \
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: "r" ((USItype)(ah)), \
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"r" ((USItype)(bh)), \
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"rI" ((USItype)(al)), \
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"r" ((USItype)(bl))); \
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} while (0)
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/* asm fragments for mul and div */
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/* umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
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* UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
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* word product in HIGH_PROD and LOW_PROD.
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*/
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#define umul_ppmm(ph, pl, m0, m1) \
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do { \
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USItype __m0 = (m0), __m1 = (m1); \
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__asm__ ("mulhwu %0,%1,%2" \
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: "=r" ((USItype)(ph)) \
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: "%r" (__m0), \
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"r" (__m1)); \
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(pl) = __m0 * __m1; \
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} while (0)
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/* udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
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* denominator) divides a UDWtype, composed by the UWtype integers
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* HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
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* in QUOTIENT and the remainder in REMAINDER. HIGH_NUMERATOR must be less
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* than DENOMINATOR for correct operation. If, in addition, the most
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* significant bit of DENOMINATOR must be 1, then the pre-processor symbol
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* UDIV_NEEDS_NORMALIZATION is defined to 1.
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*/
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#define udiv_qrnnd(q, r, n1, n0, d) \
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do { \
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UWtype __d1, __d0, __q1, __q0, __r1, __r0, __m; \
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__d1 = __ll_highpart (d); \
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__d0 = __ll_lowpart (d); \
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\
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__r1 = (n1) % __d1; \
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__q1 = (n1) / __d1; \
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__m = (UWtype) __q1 * __d0; \
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__r1 = __r1 * __ll_B | __ll_highpart (n0); \
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if (__r1 < __m) \
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{ \
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__q1--, __r1 += (d); \
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if (__r1 >= (d)) /* we didn't get carry when adding to __r1 */ \
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if (__r1 < __m) \
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__q1--, __r1 += (d); \
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} \
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__r1 -= __m; \
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\
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__r0 = __r1 % __d1; \
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__q0 = __r1 / __d1; \
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__m = (UWtype) __q0 * __d0; \
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__r0 = __r0 * __ll_B | __ll_lowpart (n0); \
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if (__r0 < __m) \
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{ \
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__q0--, __r0 += (d); \
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if (__r0 >= (d)) \
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if (__r0 < __m) \
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__q0--, __r0 += (d); \
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} \
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__r0 -= __m; \
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\
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(q) = (UWtype) __q1 * __ll_B | __q0; \
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(r) = __r0; \
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} while (0)
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#define UDIV_NEEDS_NORMALIZATION 1
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#define abort() \
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return 0
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#ifdef __BIG_ENDIAN
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#define __BYTE_ORDER __BIG_ENDIAN
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#else
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#define __BYTE_ORDER __LITTLE_ENDIAN
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#endif
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/* Exception flags. */
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#define EFLAG_INVALID (1 << (31 - 2))
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#define EFLAG_OVERFLOW (1 << (31 - 3))
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#define EFLAG_UNDERFLOW (1 << (31 - 4))
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#define EFLAG_DIVZERO (1 << (31 - 5))
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#define EFLAG_INEXACT (1 << (31 - 6))
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#define EFLAG_VXSNAN (1 << (31 - 7))
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#define EFLAG_VXISI (1 << (31 - 8))
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#define EFLAG_VXIDI (1 << (31 - 9))
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#define EFLAG_VXZDZ (1 << (31 - 10))
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#define EFLAG_VXIMZ (1 << (31 - 11))
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#define EFLAG_VXVC (1 << (31 - 12))
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#define EFLAG_VXSOFT (1 << (31 - 21))
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#define EFLAG_VXSQRT (1 << (31 - 22))
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#define EFLAG_VXCVI (1 << (31 - 23))
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