Michael J. Ruhl b53ae6bc7e IB/hfi1: set_intr_bits uses incorrect source for register modification ... HFI IRQ enable bits are not being set correctly. Send context error and DC IRQs are not being enabled correctly. In addition, send context error IRQs are not being delivered. Because of this, send context errors are not being handled correctly when they occur. When setting the IRQ bits, if an IRQ range is used, and the last bit is on a register boundary (bit 63), the calculated index for the final register modification is incorrect (index + 1 vs. index). The incorrect index calculation causes incorrect IRQ bits to be set. In this case the send context error IRQ is NOT enabled. Fix by using the 'last' value rather than the counted 'src' value to determine the final index to use. This satisfies all cases. Fixes: a2f7bbdc2d ("IB/hfi1: Rework the IRQ API to be more flexible") Reviewed-by: Mike Marciniszyn <mike.marciniszyn@intel.com> Reviewed-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com> Signed-off-by: Dennis Dalessandro <dennis.dalessandro@intel.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>		2018-09-11 11:33:13 -06:00
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core	RDMA/mlx5: Add flow actions support to raw create flow	2018-09-11 09:28:07 -06:00
hw	IB/hfi1: set_intr_bits uses incorrect source for register modification	2018-09-11 11:33:13 -06:00
sw	IB/{hfi1, qib, rdmavt}: Schedule multi RC/UC packets instead of posting	2018-09-11 09:55:02 -06:00
ulp	IB/ipoib: Ensure that MTU isn't less than minimum permitted	2018-09-06 13:35:16 -06:00
Kconfig	IB/ucm: fix UCM link error	2018-08-21 16:56:32 -06:00
Makefile	IB/rdmavt: Create module framework and handle driver registration	2016-03-10 20:37:04 -05:00